Samsung Electronics Co., Ltd.

Ki Jo Jung

Hyun Seok Cha

Ki Chul Noh

Yong Tae Jeon

Chandrashekar Tandavapura Jagadish

Yeong Kyun Lee

Vamshi Krishna Komuravelli

Ha Neul Jeong

Han Chan Jo

A data processing system includes a host capable of pipelining execution of a command set including a plurality of commands by storing the commands in a buffer, and a data storage device including a NVMe controller that receives the commands and controls execution of data access operations corresponding to the respective commands, generates a completion response upon successfully executing each one of the commands, and stores the resulting completion responses in a buffer, wherein the NVMe controller extracts at least two of the completion responses stored in the buffer to generate a completion packet and transmits the completion packet to the host during a single transaction.

Data storage device, data processing system and method of operation

A peripheral component interconnect (PCI) device includes a first memory which includes a plurality of page buffers, a base address register which includes a plurality of base addresses, and a first address translation unit which translates each of the plurality of base addresses to a corresponding one of a plurality of virtual addresses. A map table includes a plurality of map table entries each accessed in correspondence to each of the plurality of virtual addresses, and maps each of the plurality of virtual addresses onto a physical address of physical addresses of the plurality of page buffers. The first address translation unit translates each of the plurality of virtual addresses to a corresponding one of the physical addresses using the map table.

PCI device, interface system including the same, and computing system including the same

A peripheral component interconnect (PCI) device includes a PCI register including a base address register (BAR) configured to determine a first memory area accessed by a PCI host, an offset register configured to store an offset transmitted from the PCI host, an address translation unit (ATU) configured to detect an operation of the PCI host writing the offset to the offset register and to change an accessed area by the PCI host to a second memory area based on the offset stored in the offset register, and a device memory including the first memory area and the second memory area, the device memory configured to store data transmitted from the PCI host and to transmit data stored therein to the PCI host.

Peripheral component interconnect (PCI) device and system including the PCI

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Gwacheon-si, South Korea

Ki Jo Jung