Georgia Tech Research Corporation

E-system Design, Inc.

Ki Jin Han

Madhavan Swaminathan

In a method for modeling electromagnetic effects in a planar circuit that employs a plurality of through-silicon vias in a domain, a region around each through-silicon via is described in terms of a cylindrical accumulation mode basis function. The cylindrical accumulation mode basis function is incorporated into an equivalent circuit that describes selected electrical characteristics of each through-silicon via. A plurality of localized intervals around each through-silicon via is selected. A multilayer Green's function is approximated for I(wherein M and N identify selected layers and wherein zz' designates layer boundaries in a layer through which the through-silicon via passes) in each localized interval without approximating the Green's function over the entire domain. Coefficients Iare approximated over a predetermined range of frequencies (&#x3c9;). Admittance parameters based on of Iare calculated over a frequency sweep.

Modeling TSV interposer considering depletion capacitance and substrate effects

Disclosed are apparatus, methods and software that implement a partial element equivalent circuit (PEEC) method having global basis functions on cylindrical coordinates to determine wide-band resistance, inductance, capacitance, and conductance from a large number of three-dimensional interconnections in order to provide for the electrical design of system-in-package (SIP) modules, and the like. The apparatus, methods and software use a modal equivalent network from mixed potential integral equation with cylindrical conduction and accumulation mode basis functions, which reduces the matrix size for large three-dimensional interconnection problems. Combined with these modal basis functions, the mixed potential integral equations describe arbitrary skin and proximity effects, and allow determination of partial impedance and admittance values. Additional enhancement schemes further reduces the cost for computing the partial inductances. Therefore, the apparatus, methods and software can be used to construct accurate models of a large number of three-dimensional interconnection structures, including more than 100 bonding wires used for stacking integrated circuit chips, through-silicon via interconnections, and the like.

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Uslan, South Korea

Ki Jin Han