Samsung Electronics Co., Ltd.

Postech Academy-industry Foundation

Ki-jae Song

Hun-Kyo Seo

Kyoung-ho Ha

Jae-Hoon Jeong

Seong-gu Kim

Sung-Dong Suh

In-sung Joe

Soo-Haeng Cho

Chang-Woo Ko

Ung-jin Jang

Yeoung-kum Kim

Jae-Hyun Kim

Jae-il Lee

Jong-won Han

Woon-sup Choi

Joo-sung Yun

Jun-young Park

Jong-Pil Park

Sung-gu Lee

Hong-seok Yeon

A test interface board includes an encoder, a signal copier, and a decoder. The encoder digitally encodes test data to generate a modulation signal. The signal copier copies the modulation signal by inductively coupling the modulation signal and outputs at least one copy signal corresponding to the modulation signal. The decoder decodes the modulation signal and the at least one copy signal in order to test at least two semiconductor devices.

Test board, test equipment, test system, and test method

A semiconductor device and a test apparatus including the same, the semiconductor device including a command distributor receiving a serial command that is synchronized with a first clock signal and converting the serial command into a parallel command, a command decoder receiving the parallel command and generating a pattern sequence based on the parallel command, and a signal generator receiving the pattern sequence and generating operating signals synchronized with a second clock signal, wherein a frequency of the first clock signal is less than a frequency of the second clock signal.

Semiconductor device and test apparatus including the same

In a method of designing a printed circuit board, a package capacitance, a package inductance, and a chip capacitance of an actual memory device are calculated. A signal line capacitance and a signal line inductance per unit length of a signal line are calculated based on characteristics of the printed circuit board. A length of the signal line for each pin is determined based on the package capacitance and the signal line capacitance.

Package test devices having a printed circuit board

A memory test system is disclosed. The memory system includes a memory device, a tester generating a clock signal and a test signal for testing the memory device, and an optical splitting module. The optical splitting module comprises an electrical-optical signal converting unit which converts each of the clock signal and the test signal into an optical signal to output the clock signal and the test signal as an optical clock signal and an optical test signal. The optical splitting unit further comprises an optical signal splitting unit which splits each of the optical clock signal and the optical test signal into n signals (n being at least two), and an optical-electrical signal converting unit which receives the split optical clock signal and the split optical test signal to convert the split optical clock signal and the split optical test signal into electrical signals used in the memory device.

Memory system, memory test system and method of testing memory system and memory test system

A connecting unit to test a semiconductor chip and an apparatus to test the semiconductor chip having the same include a plurality of connectors, on which a semiconductor chip having a certain pattern of electrical connection terminals, having a plurality of holes, cables configured to electrically connect the electrical connection terminals to the exterior, and coupling units configured to selectively electrically connect the cables to the electrical connection terminals through the holes. Therefore, it is possible to perform electrical tests of semiconductor chips having various patterns of electrical connection terminals and receive the semiconductor chips in a tray at a time.

Connecting unit to test semiconductor chips and apparatus to test semiconductor chips having the same

Method of designing a printed circuit board

A test system may include a test device, a switching unit and/or a test board. The test device may be configured to generate a first test signal swinging between a first voltage level and a second voltage level, and the first voltage level may be lower than the second voltage level. The switching unit may be coupled to the test device, and configured to switch the first test signal to provide a second test signal swinging between a third voltage level and a fourth voltage level. The third voltage level may be lower than the fourth voltage level. A plurality of devices under test (DUTs) may be mounted on the test board. Each of the plurality of DUTs may be connected in parallel with respect to one another to the switching unit through a transmission line.

Test system

A test system includes: a tester; and a test board, on which a multi-chip package including plural memories is mounted, being connected to the tester by way of a transmission line. The transmission line includes a compensation unit for compensating signal distortion.

Test system to test multi-chip package compensating a signal distortion

Growing community of inventors

Paju-si, South Korea

Ki-jae Song