Skhynix Inc.

Hynix Semiconductor Inc.

Ki Il Moon

Jae Sung Oh

Jong Hyun Kim

Jin Ho Gwon

Young Hy Jung

Chan Sun Lee

Ki Chae Kim

Jae Youn Choi

A semiconductor package includes: a plurality of lead members disposed with a space therebetween over a surface of a substrate, a first semiconductor chip disposed in a face-up manner over the first surface of the substrate between at least two of the plurality of lead members; a second semiconductor chip disposed in a face-up manner over the first semiconductor chip and the at least two lead members, and a connection member for connecting the substrate, the at least two lead members, the first semiconductor chip and the second semiconductor chip with one another.

Semiconductor package

A stacked semiconductor package includes: a first semiconductor chip formed with a first through electrode, the first through electrode protruding above a first surface of the first semiconductor chip; a first polymer layer formed over the first surface of the first semiconductor chip such that the first through electrode is exposed by the first polymer layer; a second semiconductor chip having a first surface attached onto the first semiconductor chip by medium of the first polymer layer and a vial hole passing through the second semiconductor chip, the first surface of the second semiconductor chip being formed with a bonding pad having a through hole which corresponds to the first through electrode; and a second through electrode located within the through hole and the via hole and is electrically connected with the first through electrode.

Stacked semiconductor package and method for manufacturing the same

A substrate for a semiconductor package having a reinforcing member that prevents or minimizes distortions is presented. The substrate for the semiconductor package includes a substrate body, an insulation layer, and a reinforcing member. The substrate body has a first region having a plurality of chip mount regions, a second region disposed along a periphery of the first region, a circuit pattern disposed in each chip mount region and a dummy pattern disposed along the second region. The insulation layer covers the first and second regions and has an opening exposing some portion of each circuit pattern. The reinforcing member is disposed in the second region and prevents deflection of the substrate body.

Substrate for semiconductor package having a reinforcing member that prevents distortions and method for fabricating the same

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Yongin-si, South Korea

Ki Il Moon