Samsung Electronics Co., Ltd.

Ki-Hyun Hwang

Jae-young Ahn

Jin-Gyun Kim

Han-Mei Choi

Dong-Chul Yoo

Jun-Kyu Yang

Hun-hyeong Lim

Phil-Ouk Nam

Si-Young Choi

Bon-Young Koo

Jin-Tae Noh

Bi-O Kim

Hong-suk Kim

Dong-Kyum Kim

Sang-Hoon Lee

Ji-Hoon Choi

Seung-Jae Baik

Byong-Hyun Jang

Sang-Ryol Yang

Byong-Ju Kim

Jae-Ho Choi

Hyeon-Deok Lee

Seok-Woo Nam

Jung-Geun Jee

Hyo-Jung Kim

Jung-Hwan Oh

Su-Jin Shin

Seok-woo Nam

Ju-Yul Lee

Jung-Hwan Kim

Sang-Jin Hyun

Young-wook Park

Jae-Young Park

Eun-ha Lee

Toshiro Nakanishi

Seung-hyun Lim

Sung Heo

Joon-Suk Lee

In-Seak Hwang

Kyoung-Seok Kim

Chan-Jin Park

Chang-Won Choi

Chang-Sup Mun

Kwang-Min Park

Chang-Woo Sun

Hyung-Ik Lee

In-Sun Yi

Sung-Hae Lee

Koong-Hyun Nam

Eun-Yeoung Choi

Chang-Hyun Lee

Eun-Young Lee

Yong-Seok Kim

Woong Hee Lee

Yong-Sun Ko

Kyung-Hyun Kim

Sunghoi Hur

Jung-Hyun Park

Seung-hwan Lee

Han-jin Lim

Chul-Sung Kim

Kwangmin Park

Jung-Ho Kim

Myoung-Bum Lee

Hanmei Choi

Kwang-Soo Seol

In-seak Hwang

Tae-Gon Kim

Chanjin Park

Young-Geun Park

Jae-Jong Han

Byoung-Moon Yoon

Byung-Hong Chung

Woo-Sung Lee

Jong-Heun Lim

Hyun Namkoong

Young-jin Noh

Jin-Hwa Heo

Jong-Hoon Kang

Seung-Mok Shin

Sun-jung Kim

Won-Jun Jang

Si-Hyung Lee

Sung-hae Lee

Dong-Kak Lee

Wansik Hwang

Ju-Wan Lim

Soo-Doo Chae

Yong-Koo Kyoung

Won-sik Shin

Myung-Jung Pyo

Ju-Mi Yun

Sung-kweon Baek

Jae-Young Ahn

Hun Hyeong Lim

Sung-Ho Heo

Han-mei Choi

Bi O Kim

Young-Sub Yu

Hyun-Yong Go

A semiconductor device is provided. The semiconductor includes a plurality of interlayer insulating layers and a plurality of gate electrodes alternately stacked in a first direction on a substrate. The plurality of interlayer insulating layers and the plurality of gate electrodes constitute a side surface extended in the first direction. A gate dielectric layer is disposed on the side surface. A channel pattern is disposed on the gate dielectric layer. The gate dielectric layer includes a protective pattern, a charge trap layer, and a tunneling layer. The protective pattern includes a portion disposed on a corresponding gate electrode of the plurality of gate electrodes. The charge trap layer is disposed on the protective pattern. The tunneling layer is disposed between the charge trap layer and the channel pattern. The protective pattern is denser than the charge trap layer.

Semiconductor device and method of fabricating the same

Tunnel insulation layer structures and methods of manufacturing the same are disclosed. The tunnel insulation layer structures may include a first tunnel insulation layer, a second tunnel insulation layer, a third tunnel insulation layer, a fourth tunnel insulation layer and a fifth tunnel insulation layer. The first tunnel insulation layer on a substrate has a first band gap energy. The second tunnel insulation layer on the first tunnel insulation layer has a second band gap energy which is lower than the first band gap energy. The third tunnel insulation layer on the second tunnel insulation layer has a third band gap energy which is higher than the second band gap energy. The fourth tunnel insulation layer on the third tunnel insulation layer has a fourth band gap energy which is lower than the third band gap energy. The fifth tunnel insulation layer on the fourth tunnel insulation layer has a fifth band gap energy which is higher than the fourth band gap energy.

Tunnel insulation layer structures, methods of manufacturing the same, and vertical memory devices including the same

In a method of forming an oxide layer of a semiconductor process, a preliminary precursor flow is provided on a substrate in a deposition chamber to form a preliminary precursor layer, a precursor flow and a first oxidizing agent flow are provided on the preliminary precursor layer alternately and repeatedly to form precursor layers and first oxidizing agent layers alternately stacked on the preliminary precursor layer, and a second oxidizing agent flow is provided on the precursor layer or the first oxidizing agent layer alternately stacked to form a second oxidizing agent layer.

Methods of manufacturing semiconductor devices including an oxide layer

Three-dimensional semiconductor memory devices and methods of fabricating the same. The three-dimensional semiconductor devices include an electrode structure with sequentially-stacked electrodes disposed on a substrate, semiconductor patterns penetrating the electrode structure, and memory elements including a first pattern and a second pattern interposed between the semiconductor patterns and the electrode structure, the first pattern vertically extending to cross the electrodes and the second pattern horizontally extending to cross the semiconductor patterns.

Three-dimensional semiconductor memory devices and methods of fabricating the same

A non-volatile memory device having a vertical structure includes a semiconductor layer, a sidewall insulation layer extending in a vertical direction on the semiconductor layer, and having one or more protrusion regions, first control gate electrodes arranged in the vertical direction on the semiconductor layer, and respectively contacting one of portions of the sidewall insulation layer where the one or more protrusion regions are not formed and second control gate electrodes arranged in the vertical direction on the semiconductor layer, and respectively contacting one of the one or more protrusion regions.

Non-volatile memory device having a vertical structure and method of fabricating the same

A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes insulation layers and gate electrodes alternately stacked on a substrate, a vertical channel vertically passing through the insulation layers and the gate electrodes, and a threshold voltage controlling insulation layer, a tunnel insulation layer and a charge storage layer disposed between the vertical channel and the gate electrodes, wherein the threshold voltage controlling insulation layer is disposed between the charge storage layer and the vertical channel and including a material configured to suppress an inversion layer from being formed in the vertical channel.

Semiconductor memory device and method of manufacturing the same

A method of manufacturing a vertical memory device includes forming alternating and repeating insulating interlayers and sacrificial layers on a substrate, the sacrificial layers including polysilicon or amorphous silicon, forming channel holes through the insulating interlayers and the sacrificial layers, forming channels in the channel holes, etching portions of the insulating interlayers and the sacrificial layers between adjacent channels to form openings, removing the sacrificial layers to form gaps between the insulating interlayers, and forming gate lines in the gaps.

Vertical memory devices and methods of manufacturing the same

Nonvolatile memory devices include at least four cylindrical-shaped channel regions, which extend vertically from portions of a substrate located at respective vertices of at least one rhomboid when viewed in a vertical direction relative to a surface of the substrate. A charge storage layer (e.g., ONO layer) is provided on an outer sidewall of each of the cylindrical-shaped channel regions. In addition, to achieve a high degree of integration, a plurality of vertically-stacked gate electrodes are provided, which extend adjacent each of the cylindrical-shaped channel regions.

A vertical memory device includes a channel array, a charge storage layer structure, multiple gate electrodes and a dummy pattern array. The channel array includes multiple channels, each of which is formed on a first region of a substrate and is formed to extend in a first direction substantially perpendicular to a top surface of the substrate. The charge storage layer structure includes a tunnel insulation layer pattern, a charge storage layer pattern and a blocking layer pattern, which are sequentially formed on a sidewall of each channel in the second direction substantially parallel to the top surface of the substrate. The gate electrodes arranged on a sidewall of the charge storage layer structure and spaced apart from each other in the first direction. The dummy pattern array includes multiple dummy patterns, each of which is formed on a second region adjacent the first region of the substrate and is formed to extend in the first direction.

Memory devices and methods of manufacturing the same

A vertical memory device including a substrate including first regions and a second region; a plurality of channels in the first regions, the plurality of channels extending in a first direction substantially perpendicular to a top surface of the substrate; a charge storage structure on a sidewall of each channel in a second direction substantially parallel to the top surface of the substrate; a plurality of gate electrodes in the first regions, the plurality of gate electrodes arranged on a sidewall of the charge storage structure and spaced apart from each other in the first direction; and a plurality of supporters in the second region, the plurality of supporters spaced apart from each other in a third direction substantially perpendicular to the first direction and the second direction, the plurality of supporters contacting a sidewall of at least one gate electrode.

A method of manufacturing a vertical memory device is disclosed. In the method, a plurality of insulation layers and a plurality of first sacrificial layers are alternately stacked on a substrate. A plurality of holes is formed through the plurality of insulation layers and first sacrificial layers. A plasma treatment process is performed to oxidize the first sacrificial layers exposed by the holes. A plurality of second sacrificial layer patterns project from sidewalls of the holes. A blocking layer pattern, a charge storage layer pattern and a tunnel insulation layer pattern are formed on the sidewall of the holes that cover the second sacrificial layer patterns. A plurality of channels is formed to fill the holes. The first sacrificial layers and the second sacrificial layer patterns are removed to form a plurality of gaps exposing a sidewall of the blocking layer pattern. A plurality of gate electrodes is formed to fill the gaps.

Vertical memory devices and method of manufacturing the same

According to example embodiments of inventive concepts, a method of fabricating a semiconductor device includes: forming a preliminary stack structure, the preliminary stack structure defining a through hole; forming a protection layer and a dielectric layer in the through hole; forming a channel pattern, a gapfill pattern, and a contact pattern in the through hole; forming an offset oxide on the preliminary stack structure; measuring thickness data of the offset oxide; and scanning the offset oxide using a reactive gas cluster ion beam. The scanning the offset oxide includes setting a scan speed based on the measured thickness data of the offset oxide, and forming a gas cluster.

Method of fabricating semiconductor device having preliminary stacked structure with offset oxide etched using gas cluster ion

According to example embodiments, a semiconductor device includes horizontal patterns stacked on a substrate. The horizontal patterns define an opening through the horizontal patterns. A first core pattern is in the opening. A second core pattern is in the opening on the first core pattern. A first active pattern is between the first core pattern and the horizontal patterns. A second active pattern containing a first element is between the second core pattern and the horizontal patterns. The second active pattern contains the first element at a higher concentration than a concentration of the first element in the second core pattern.

Semiconductor device including a first core pattern under a second core pattern

A method of forming a polysilicon layer includes providing a silicon precursor onto an object loaded in a process chamber to form a seed layer. The silicon precursor includes a nitrogen containing silicon precursor and a chlorine containing silicon precursor. The method further includes providing a silicon source on the seed layer.

Methods of forming a polysilicon layer and methods of manufacturing semiconductor devices

Growing community of inventors

Seongnam-si, South Korea

Ki-Hyun Hwang