Samsung Display Co., Ltd.

Samsung Electronics Co., Ltd.

Ki-Hyuk Kim

Hyun-Soo Chung

Seung-Ho Nam

Seong-Mo Hwang

Hyun-Ju Lee

Il-Ho Lee

Ji-Hong Park

Moon-Sung Choi

In-Cheol Kim

Ji-Yong Park

Sung-Ho Cho

Seong-deok Hwang

Seok-Ho Kim

Myeong-Soon Park

Donghan Kim

Sung-Jin Kim

Sang-Hyun Lee

Jin-Won Lee

Nam-seog Kim

Dong-ho Lee

Nam-Hee Goo

Chang-Woo Shin

Jum-Gon Kim

Jae-Shin Cho

Jin-Kuk Bae

Yong-cheol Seo

Chang-woo Shin

Seuk-Whan Lee

A sensor substrate includes a base substrate, a black matrix pattern, a sensing electrode pattern, a driving electrode pattern, and at least one bridge line. The black matrix pattern is disposed on the base substrate and divides the base substrate into a light transmission area and a light blocking area. The sensing electrode pattern includes a plurality of first unit patterns arranged in association with a first direction. The driving electrode pattern includes a plurality of second unit patterns arranged in association with a second direction and disposed adjacent to the plurality of first unit patterns. The at least one bridge line is connected between at least two of the plurality of first unit patterns or between at least two of the plurality of second unit patterns.

Sensor substrate and sensing display panel having the same

A display panel and display device having the same are disclosed. In one aspect, the display panel includes a first substrate including a display region configured to display images and a non-display region surrounding the display region. The display panel further includes a metal pattern disposed in the non-display region, a second substrate opposing the first substrate, and a sealant disposed between and substantially sealing the first and second substrates, wherein the sealant at least partially overlaps the metal pattern. The metal pattern includes a body portion surrounding the display region and a plurality of protrusions extending from the body portion in a direction from the display region to the non-display region.

Display panel and display device having the same

A spark-preventing element embedded in a printed circuit board includes a capacitive output electrode, a capacitive input electrode, an interlayer conductive member electrically connecting the capacitive output electrode to a signal line, and an interlayer insulation member electrically insulating the capacitive input electrode from the signal line, The capacitive input electrode is spaced apart from the capacitive output electrode with an air gap disposed between the capacitive output electrode and the capacitive input electrode, surrounds the capacitive output electrode, and is electrically connected to the ground layer. The spark-preventing element has an improved electrical characteristic and an increased durability.

Spark preventing element for printed circuit board

A semiconductor device includes a semiconductor substrate including a main chip region and a remaining scribe lane region surrounding the main chip region, a passivation layer on the main chip region, the passivation layer including a plurality of bridge patterns extending from the main chip region in a first direction across the remaining scribe lane region, a plurality of bump pads exposed by the passivation layer on the main chip region, a plurality of dam structures along edges of the main chip region on the remaining scribe lane region, the plurality of bridge patterns arranged on the plurality of dam structures at a first pitch in the first direction, a seed layer on the plurality of bump pads, and bumps on the seed layer.

Semiconductor device

Semiconductor devices and methods of forming the same, including forming a chip pad on a chip substrate, forming a passivation layer on the chip pad and the chip substrate, forming a first insulation layer on the passivation layer, forming a recess and a first opening in the first insulation layer, forming a second opening in the passivation layer to correspond to the first opening, forming a redistribution line in a redistribution line area of the recess, the first opening, and the second opening, forming a second insulation layer on the redistribution line and the first insulation layer, and forming an opening in the second insulation to expose a portion of the redistribution line as a redistribution pad.

Semiconductor devices having redistribution structures and packages, and methods of forming the same

A semiconductor package may have a semiconductor chip that includes a chip pad formed on a substrate including an integrated circuit, and a passivation layer exposing the chip pad, a first redistribution wiring layer that is connected to the chip pad and extends on the semiconductor chip and includes a wire bonding pad to provide wire bonding and a first solder pad to connect the first redistribution wiring layer to a second semiconductor chip, and a second redistribution wiring layer that is connected to the first redistribution wiring layer on the first redistribution wiring layer and includes a second solder pad to connect the second redistribution wiring layer to a third semiconductor chip.

Semiconductor package and multi-chip package using the same

A semiconductor module can include a printed circuit board (PCB) and a semiconductor package inserted into an inner space of the PCB. The semiconductor package may be electrically connected to the PCB. The PCB may thus surround the semiconductor package so that cracks may not be generated in the outer terminals.

Semiconductor module

A semiconductor package with improved joint reliability and a method of fabricating the semiconductor package are disclosed. A conductive connector may be formed on a surface of a semiconductor wafer on which semiconductor devices may be arranged. A first insulating layer including a first opening through which a portion of the connection pad is exposed may be formed on the connection pad and the semiconductor wafer. A rewiring line electrically connected to an exposed portion of the connection pad may be formed on the first insulating layer. A second insulating layer including a second opening through which a portion of the rewiring line is exposed may be formed on the rewiring line and the first insulating layer. A connection terminal including one or more entangled wires may be formed on an exposed portion of the rewiring line so as to be electrically connected to the rewiring line.

Semiconductor package with joint reliability, entangled wires including insulating material

Growing community of inventors

Yongin-si, South Korea

Ki-Hyuk Kim