Samsung Electronics Co., Ltd.

Ki-ho Shin

Sung-il Cho

Byung-Joon Moon

Jong-Soo Seo

An improved surge protecting circuit which can protect the power source and the internal and external circuit elements of an electronic product by absorbing external surges through ground. The protecting circuit according to the present invention is connected between an AC input terminal and an AC ground pattern. The protecting circuit includes surge absorption patterns having an arc discharge gap of preferably 0.25 mm, which is less than a specified safety distance, which is typically 5 mm, so as to absorb the external surges transmitted through the terminal to the AC ground pattern and a varistor connected between the surge absorption patterns and the AC ground patterns.

Electronic products with improved surge protecting circuit

A reproduction error correction circuit for a video reproduction system includes a line-storage memory for temporarily storing composite video signal samples, which memory is operated to provide both for time-base correction and for drop-out compensation. The memory is cyclically supplied sequential write addresses descriptive of pixel locations along a horizontal scan line, generated at a rate that tracks any jitter in the input video signal selectively used for writing over the previous contents of the memory. The memory is cyclically supplied sequential read addresses offset 1/2 scan line from the write addresses, generated at a stable rate equal to an average over several scan lines of the rate at which write addresses are generated. This provides for time-base error correction. When a drop-out is detected, overwriting of video signal samples already stored in the single line-storage memory is prohibited. This type of overwrite protection implements automatic replacement of the video signal during periods when drop-out is detected. The phase of the chrominance signal component of the delayed video used for drop-out compensation is adjusted, however, when necessary, to correspond to that required in the replacement signal.

Reproduction error correction circuit for a video reproduction system,

Reproduction error correction circuit for a video reproduction system &

A circuit for detecting the recording/playback mode of a system, e.g., a video tape recorder (VTR), for recording/playing back an image signal on/from a recording medium, using first and second input signals derived from pilot signals also recorded on the recording medium. The circuit includes a first peak value detector for detecting the peak value of the first input signal, and for generating a first output signal representative of the peak value of the first input signal, and a second peak value detector for detecting the peak value of the second input signal, and for generating a second output signal representative of the peak value of the second input signal. The circuit further includes a comparator for comparing the first output signal and the second output signal, and for generating a comparison output signal representative of the difference therebetween and, a mode discrimination signal generating circuit, responsive to the comparison output signal, for generating a mode discrimination signal indicative of the recording mode that the image signal was recorded in, and the playback mode that the image signal is being played back in.

Mode discrimination circuit for an image recording/playback system

A data coincidence detecting circuit including a register for receiving n-bit data, a counter for counting up until 2.sup.n to compare the n-bit data with it, a comparator for comparing the outputs of the register and the outputs of the counter, respectively to generate a coincidence detecting signal, a mask portion connected to the output of the comparator for masking the period from a time point when the n-bit data is input to a time point when the input of data ends, and a logic circuit for logically adding the output of the mask portion and the output of the comparator to output the result.

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Kyungki-do, South Korea

Ki-ho Shin