Hynix Semiconductor Inc.

Skhynix Inc.

Hybix Semiconductor, Inc.

Ki-Ho Kim

Young-Jun Ku

Ji-Eun Jang

Seok-Cheol Yoon

Kee-Teok Park

Chang-Ho Do

Sang-Jin Byeon

Chun-Seok Jeong

Kyung-Whan Kim

Kang-Seol Lee

A test apparatus includes a test apparatus may include a core suitable for accommodating a semiconductor device to be tested, a wrapper data register suitable for storing data used for testing the semiconductor device, and a bandwidth controller suitable for adaptively controlling a data bandwidth between the core and the wrapper data register according to the semiconductor device to be tested.

Test apparatus and operating method thereof

A semiconductor memory device includes a plurality of banks, a plurality of compression blocks configured to compress a plurality of first read data respectively provided by the banks and output a plurality of second read data, a plurality of pipe latches configured to latch the second read data and output third read data in series, an output controller configured to receive the third read data from the pipe latches and sequentially output fourth read data in response to a plurality of bank addresses and a read enable signal, and a pad configured to transfer the fourth read data sequentially outputted from the output controller to an outside of the semiconductor memory device.

Semiconductor memory device

A semiconductor memory device includes a pad configured to receive a first write data from outside of the semiconductor memory device, and a write circuit configured to generate a plurality of second write data which are to be written in memory cells of all banks to be tested in response to a test mode signal, data strobe signals, a write enable signal, and the first write data transferred through the pad.

A semiconductor memory device includes a read circuit configured to sequentially output a plurality of compressed data corresponding to all banks which are to be tested in response to a plurality of bank addresses and a read enable signal during a test mode and a pad configured to transfer the compressed data which are sequentially outputted from the read circuit to an outside of the semiconductor memory device.

A data input device of a semiconductor memory apparatus includes: a differential amplifier configured to compare an input to a reference voltage and output a differential signal based on the comparison; and a control circuit configured to adjust a current driving capacity of the differential amplifier by turning on a first current path connected to the differential amplifier in response to a first enable signal and turning off a second current path connected to the differential amplifier in response to a second enable signal in a standby mode, wherein, during a time that a plurality of external command signals toggle back and forth between a status of all being high signals and a status of all being low signals repeatedly, the second enable signal is controlled to be maintained at a low state signal.

Data input device of semiconductor memory appartus and control method thereof

A semiconductor memory device includes a data input driver and a data output driver for receiving an external power supply voltage, and for inputting and outputting data, respectively; and a voltage detector for detecting the external power supply voltage to generate a detection signal, wherein a drive current of each of the data input driver and the data output driver is controlled by the detection signal.

Semiconductor memory device and driving method thereof

A calibration circuit of an on-die termination device includes a code generating unit configured to receive a voltage of a calibration node connected to an external resistor and a reference voltage to generate pull-up calibration codes. The calibration circuit also includes a pull-up calibration resistor unit configured to pull up the calibration node in response to the pull-up calibration codes. The pull-up calibration resistor unit is calibrated such that its resistance becomes higher as a power supply voltage increases.

Calibration circuit of on-die termination device

A delay locked loop circuit includes a delay locking block configured to delay an input clock and output the delayed input clock as an internal clock to compensate a skew of an external clock and the internal clock, a pulse generating block configured to sequentially output a plurality of pulse signals that control an operation of the delay locking block and enable one of the plurality of pulse signals in response to a detection signal, wherein the plurality of pulse signals is shifted by being synchronized with the input clock, and a pulse detecting block configured to output the detection signal in case all of the plurality of pulse signals are disabled.

Delay locked loop circuit

A semiconductor memory device is capable of outputting calibration codes to an external circuit. The semiconductor memory device includes a data output control unit for controlling an output of data, a calibration code output control unit for transmitting calibration codes to determine a termination resistance value, a test mode signal generating unit for generating a test mode signal which is enabled in the test mode for outputting the calibration codes, and a test mode control unit for selectively outputting the data or the calibration codes in response to the test mode signal.

Semiconductor memory device with ZQ calibration

An impedance adjusting circuit includes: a calibration circuit configured to generate a first calibration code and a second calibration code for determining termination resistance; a transmission line circuit configured to transfer the first calibration code during a first section and to transfer the second calibration code during a second section; and a termination resistor circuit adapted to match an impedance with a resistance determined by receiving the first and second calibration codes.

Impedance adjusting circuit and semiconductor memory device having the same

On die termination (ODT) device that can reduce the number of lines for transferring calibration codes to reduce the size of a chip including the ODT device. The ODT device includes a calibration circuit configured to generate calibration codes for determining a termination resistance, a counting circuit configured to generate counting codes increasing with time. A transferring circuit of the device is configured sequentially to transfer the calibration codes in response to the counting codes. A receiving circuit is configured sequentially to receive the calibration codes from the transferring circuit in response to the counting codes. A termination resistance circuit of the device is configured to perform impedance matching using a resistance determined according to the calibration codes.

On die termination device and semiconductor memory device including the same

An impedance matching circuit performs a ZQ calibration for a test on a wafer process of a semiconductor memory device. The impedance matching circuit of the semiconductor memory device includes a first pull-down resistance unit, a first pull-up resistance unit, a second pull-up resistance unit and a second pull-down resistance unit. The first pull-down resistance unit supplies a ground voltage to a first node in response to a calibration test signal. The first pull-up resistance unit calibrates its resistance to that of the first pull-down resistance unit to thereby generate a pull-up calibration code. The second pull-up resistance unit supplies a supply voltage to a second node in response to the pull-up calibration code. The second pull-down resistance unit calibrates its resistance to that of the second pull-up resistance unit to thereby generate a pull-down calibration code.

Impedance matching circuit and semiconductor memory device with the same

A semiconductor device includes a pad configured to receive a data strobe signal, and a path selector configured to output the data strobe signal through a corresponding input path during a normal operation, and to output the data strobe signal through a plurality of input paths in response to a path selection signal during a test operation.

Semiconductor device and operating method thereof

A ZQ calibration circuit performs a ZQ calibration additionally in an initial operation of a semiconductor memory device. The ZQ calibration controller of the ZQ calibration circuit includes a first signal generator, a second signal generator, and a control unit. The first signal generator generates a pre-calibration signal during an initialization of the semiconductor memory device. The second signal generator generates ZQ calibration signals in response to a ZQ calibration command. The control unit outputs signals to control a ZQ calibration in response to the pre-calibration signal and the ZQ calibration signals.

ZQ calibration controller and method for ZQ calibration

A probe-testing device includes probe tips configured to apply inputs to pads of a semiconductor chip, wherein one of the probe tips is connected to a calibration pad for impedance adjustment and a calibration resistor is connected thereto.

Growing community of inventors

Kyoungki-do, South Korea

Ki-Ho Kim