Samsung Electronics Co., Ltd.

Ki Heung Kim

Reum Oh

Moon Hee Oh

Jun Gyu Lee

In Chul Jeong

According to some embodiments, for a memory device including a base die and a stack of memory dies including a plurality of memory dies stacked on the base die, the base die including a plurality of first input/output (i/o) terminals that are command/address and data terminals and a plurality of second i/o terminals that are direct access terminals, a method includes receiving at the plurality of first i/o terminals a command/address, a clock signal, and data; first transmitting the command/address, clock signal, and data received by the plurality of first i/o terminals from the base die to the stack of memory dies; and second transmitting at least part of one or more of the command/address, clock signal, and data received by a set of the plurality of first i/o terminals through a circuit of the base die to the plurality of second i/o terminals.

High bandwidth memory device and system device having the same

According to some embodiments, a high bandwidth memory device includes a base die and a plurality of memory dies stacked on the base die and electrically connected to the base die through a plurality of through substrate vias. The base die includes a plurality of first input buffers configured to receive channel clock signals, channel command/addresses, and channel data from a plurality of first bumps connected to the outside of the base die, a plurality of second input buffers configured to receive test clock signals, test command/addresses, and test data from a plurality of second bumps connected to the outside of the base die, a monitoring unit, a plurality of first output buffers connected to the monitoring unit and configured to output monitored data from the monitoring unit to the plurality of second bumps, and a plurality of paths from the plurality of first input buffers to the monitoring unit. The plurality of second bumps are connected to receive test clock signals, test command/addresses, and test data from the outside of the base die during a first operation mode, and to receive monitored data from the plurality of first output buffers during a second operation mode.

A method of repairing a word line of a memory device includes receiving a row address, comparing a received row address with a row address of a defective cell, enabling a normal word line and a redundant word line, which correspond to the row address, according to a result of the row address comparison, receiving a column address, comparing a received column address with a column address of the defective cell, and performing a memory access operation on one of the normal word line and the redundant word line according to a result of the column address comparison.

Memory device, operation method thereof, and memory system having the same

A memory refresh method includes selecting at least one bank from among N banks of a memory device, and activating K word lines from among a plurality of word lines included in the at least one bank during one of L refresh cycles of a refresh period. Each of the N banks comprises M word lines, N, K and M are each a natural number greater than or equal to two, L is a natural number less than or equal to M, and K is equal to M*N/L.

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Hwaseong-si, South Korea

Ki Heung Kim