Samsung Electronics Co., Ltd.

Hyundai Motor Company

Infineon Technologies Ag

Sejong Ind. Co., Ltd

Ki-Chul Park

Seung-Man Choi

Se-Hee Han

Joo-Yeol Lee

Yong-jin Kim

Kyoung-woo Lee

Chang-Sub Lee

Jung-Woo Kim

Won-sang Song

Soo-Geun Lee

Sam-Young Kim

Young-Jin Wee

Joon-Oo Kim

Won-Sang Kwon

Il-Ryong Kim

Je-Young Maeng

Ja-hum Ku

Ho-Yong Jung

Ja-Hum Ku

Hong-uk Woo

Seung-man Choi

Bong-Seok Suh

Sun-Jung Lee

Jong-won Kim

Mu-kyeng Jung

Byung-Soo Lim

Hyungwoo Kim

Tae-hwan Hwang

Kyoung-Woo Lee

Ji-Hyeok Kim

Sang-Won Ahn

In-Sung Jung

Sangman Lee

Seung-Hoon Chae

Sun Oo Kim

Young Min Kang

Ming Jin

Ju-Hyuck Lee

Hong-Jae Kim

Hun-Seop Jeong

Ji-Young Yang

Young-Jin Sung

An apparatus, method, and system for providing information for a wireless network connection using Wi-Fi. Device information for at least one UPnP device is provided from a plurality of wireless devices including the at least one UPnP device, a device information announcement message including the device information for the at least one UPnP device is generated, and the generated device information announcement message is broadcasted. In this way, information on a UPnP device to which to connect a wireless device is provided in advance, and a user can easily perform a network connection.

Apparatus and method for providing information for a wireless network connection using Wi-Fi

A structure pof muffler may include a housing which has a space therein, and has a first side connected to an inlet pipe into which exhaust gas flows, a first baffle which divides an interior of the housing into a front chamber and an intermediate chamber connected to the inlet pipe, a second baffle which divides the interior of the housing into a rear chamber and the intermediate chamber connected to the inlet pipe, and a discharge pipe which is mounted to penetrate the first baffle and the second baffle, and mounted such that a first end of the discharge pipe is positioned in the rear chamber, and a second end of the discharge pipe extends through the front chamber and penetrates the housing.

Structure of muffler

A method and apparatus for changing an input type in an input system using UPnP are provided. A control point requests input capability information of input devices, which are to perform input and receives the input capability information. The control point sets up a session by determining a receiving device for receiving an input signal and a transmitting device for transmitting the input signal, using the received input capability information. The receiving device receives input data from the transmitting device, and if an input type of the receiving device is changed, the receiving device transmits information about the changed input type to the transmitting device and receives a report descriptor including information about a format of input data according to the changed input type from the transmitting device.

Method and apparatus for changing input type in input system using universal plug and play

A Digital Living Network Alliance (DLNA) system and method of providing content therein are provided. A legacy media player displays a content list for content stored in the legacy media player or in an add-in server, and when a content item is selected from the list, the legacy media player determines whether the content item is reproducible by a registered digital media renderer. If the selected content item is reproducible by the registered digital media renderer, the legacy media player transmits a reproducing request for the selected content item, and the corresponding digital media renderer receives and reproduces the selected content.

Digital living network alliance system and method for providing content therein

Disclosed is a method of fabricating a semiconductor chip. The method includes forming a silicon layer; forming a first layer formed on the silicon layer and including a first seal ring surrounding a first chip area and a second seal ring surrounding a second chip area; and forming a second layer formed on the first layer and including a metal interconnection connecting one of the first and second chip areas and an external terminal.

Semiconductor chip including a plurality of chip areas and fabricating method thereof

A method of forming a wiring layer of a semiconductor device, includes forming a first interlayer insulating layer to have a first thickness corresponding to a part of the thickness of an interlayer insulating layer that is to be formed on a support layer and forming a first contact plug in the first interlayer insulating layer. The method further includes forming a second interlayer insulating layer to have a second thickness on the first contact plug and the first interlayer insulating layer, thereby forming the interlayer insulating layer, wherein the second thickness corresponds to the rest of the thickness of the interlayer insulating layer, and forming a second contact plug connected to the first contact plug in the second interlayer insulating layer, thereby forming a local wiring layer including the first contact plug and the second contact plug.

Method of forming wiring layer of semiconductor device

Methods are provided for forming dual damascene interconnect structures using different conductor materials to fill via holes and line trenches. For example, a method for forming an interconnection structure includes depositing dielectric material on a semiconductor substrate and etching the dielectric material to form a dual damascene recess structure including a via hole and trench. A layer of first conductive material is then conformally deposited to fill the via hole with the first conductive material, and the layer of first conductive material is etched to remove the first conductive material from the trench and an upper region of the via hole below the trench. A layer of second conductive material is then deposited to fill the trench and upper region of the via hole with the second conductive material.

Methods for forming damascene wiring structures having line and plug conductors formed from different materials

An image sensor device and method for forming the same include a photodiode formed in a substrate, at least one electrical interconnection line electrically associated with the photodiode, a light passageway having a light inlet, the light passageway being positioned in alignment with the photodiode, a color filter positioned over the light inlet of the light passageway and a lens positioned over the color filter in alignment with the light passageway wherein the at least one electrical interconnection line includes a copper interconnection formation having a plurality of interlayer dielectric layers in a stacked configuration with a diffusion barrier layer between adjacent interlayer dielectric layers, and a barrier metal layer between the copper interconnection formation and the plurality of interlayer dielectric layers and intervening diffusion barrier layers. An image sensor device may employ copper interconnections if a barrier metal layer is removed from above a photodiode.

Structure of a CMOS image sensor and method for fabricating the same

Methods of forming integrated circuit devices include patterning an electrically insulating layer to support dual-damascene interconnect structures therein. The steps of patterning the electrically insulating layer include using multiple planarization layers having different porosity characteristics. Forming an interconnect structure within an integrated circuit device may include forming an electrically insulating layer on a substrate and forming at least one via hole extending at least partially through the electrically insulating layer. The at least one via hole is filled with a first electrically insulating material having a first porosity. The filled at least one via hole is then covered with a second electrically insulating material layer having a second porosity lower than the first porosity. The second electrically insulating material layer is selectively etched back to expose a first portion of the first electrically insulating material in the at least one via hole. The electrically insulating layer is selectively etched to define a trench therein that exposes a second portion of the first electrically insulating material in the at least one via hole.

Methods of forming dual-damascene interconnect structures on semiconductor substrates using multiple planarization layers having different porosity characteristics

In a method of fabricating a semiconductor device by selectively forming a diffusion barrier layer, and a semiconductor device fabricated thereby, a conductive pattern and an insulating layer, which covers the conductive pattern, are formed on a semiconductor substrate. The insulating layer is patterned, thereby forming an opening for exposing at least a portion of the conductive pattern. Then, a diffusion barrier layer is formed on the semiconductor substrate having the opening, using a selective deposition technique. The diffusion barrier layer is formed to a thickness that is less on the exposed conductive pattern than the thickness of the diffusion barrier layer on the insulating layer exposed inside the opening. Then, the diffusion barrier layer is etched, thereby forming a recessed diffusion barrier layer. In this manner, metal atoms are prevented from being diffused from a metal plug filling the opening or a metal interconnect to the insulating layer.

Method of fabricating semiconductor device by forming diffusion barrier layer selectively and semiconductor device fabricated thereby

In a MIM capacitor, and method of fabricating the same, the MIM capacitor includes an interlayer insulating layer on a semiconductor substrate, a lower metal interconnection and a lower metal electrode in the interlayer insulating layer, an intermetal dielectric layer covering the lower metal interconnection, the lower metal electrode, and the interlayer insulating layer, a via hole exposing the lower metal interconnection, an upper metal interconnection groove crossing over the via hole, at least one capacitor trench region exposing the lower metal electrode, an upper metal interconnection filling the upper metal interconnection groove, the upper metal interconnection being electrically connected to the lower metal interconnection through the via hole, a dielectric layer covering inner surfaces of the at least one capacitor trench region, and an upper metal electrode surrounded by the dielectric layer to fill the at least one capacitor trench region.

Metal-insulator-metal (MIM) capacitor and method of fabricating the same

A semiconductor device includes a lower copper line formed on a substrate, an interlayer insulating layer formed on the lower copper line, and an upper copper line formed on the interlayer insulating layer. A copper via contact extends through the interlayer insulating layer for electrically connecting the lower copper line and the upper copper line. A concave recess is formed within the lower copper line and is vertically aligned and arranged below the copper via contact. A patterned barrier layer is formed at a bottom portion of the concave recess, such that the lower copper line and the copper via contact are directly electrically connected at an interface along sides of the concave recess, without an intervening barrier layer.

Semiconductor device having multi-layer copper line and method of forming same

In the present invention, an apparatus of testing a leakage protection reliability of an integrated circuit interconnection. The apparatus has at least one comb-like pattern, a serpentine-like pattern and means of applying a bias to the patterns and forms a maximum field region at an interconnection formed around a via, i.e., at the end of a tooth portion composing the comb-like pattern. In one structure of the present invention, the comb-like pattern is formed at one level, and the serpentine-like pattern has a plurality of unit parts corresponding to the tooth portions, respectively, and connection parts connecting the neighboring two unit parts. Each of the unit parts is formed at the same level with the comb-like pattern and spaced apart from the tooth portion by a minimum design length according to a design rule. The unit part has vias formed through an interlayer dielectric layer at the both ends of a tooth parallel part, two tooth parallel parts connected with the vias, respectively, and a length parallel part electrically connecting two tooth parallel parts.

Apparatus for testing reliability of interconnection in integrated circuit

Growing community of inventors

Suwon-si, South Korea

Ki-Chul Park