Samsung Electronics Co., Ltd.

Ki-Bong Ju

Jeong-Ho Bang

Hyun-Seop Shim

Hyoung-Young Lee

Hyuk Jae Kwon

Young-Gu Shin

Kyoung-Il Heo

Young-Ki Kwak

Woo-Il Kim

A test apparatus for testing a multi-chip package comprising a multiplicity of semiconductor chips, which includes a test driver having one drive channel and at least one input/output channel. A test board is mounted with the multi-chip package. Drive pins of the semiconductor chips are parallel connected to the drive channel, and input/output pins of the semiconductor chips are parallel connected to the input/output channel.

Multichip package test

Embodiments of the invention connect a plurality of devices under test (DUTS) in a parallel manner and a high test current is selectively applied to each DUT. The apparatus to test a plurality of DUTs includes a plurality of power sources providing the test current to a plurality of DUTs; and switching devices connected to the respective DUTs and power sources and selectively providing the test current. In addition, the apparatus has at least one control unit to control the switching devices. Furthermore, a group of DUTs from the plurality of DUTs is connected between two of the plurality of power sources in a parallel manner, and the test current is selectively provided to one DUT from the group of DUTs according to the operation of the switching devices.

Apparatus and method for performing parallel test on integrated circuit devices

Growing community of inventors

Choongchungnam-do, South Korea

Ki-Bong Ju