Cypress Semiconductor Corporation

Matrix Semiconductor, Inc.

Sandisk 3d LLC

Sandisk Corporation

Khushrav S Chhor

Vani Verma

William R Orso

Tae-Hee Lee

Larry Louis Moresco

Bo Soon Chang

Timothy M Lacey

Joseph D Caliston

By decreasing the amount of card substrate required in a memory card to support the actual memory unit, the test interface of the card, which is usually removed before final assembly of the card, can be brought within the allowable length of the finished card and can, therefore, remain on the card permanently. Consequently, in the event of a field failure, the test interface remains available for testing the card and diagnosing the location and cause of the failure.

Methods of making and using memory card with enhanced testability

A multi-chip memory module may be formed including two or more stacked integrated circuits mounted to a substrate or lead frame structure. The memory module may include means to couple one or more of the stacked integrated circuits to edge conductors in a memory card package configuration. Such means may include the capability to utilize bonding pads on all four sides of an integrated circuit. A lead frame structure may be divided into first and second portions. The first portion may be adapted to receive the stacked integrated circuits and the second portion may include a plurality of conductors. The first portion may also be adapted to couple at least one of the integrated circuits to power and ground conductors on the second portion. In one embodiment, the first portion may include the lead frame paddle and a conductive ring. In another embodiment, the first portion may include first and second coplanar elements.

Memory module having interconnected and stacked integrated circuits

Memory card with enhanced testability and methods of making and using the same

An improved memory module and method of manufacture are presented. The memory module takes on the same outer dimensions as conventional memory cards. The memory module includes an integrated circuit and a conductor encased within molded resin. The conductor can be taken from a tape or a lead frame, and can include bumps or wires extending from the conductor to corresponding bonding pads on the integrated circuit. The bonded integrated circuit can thereafter be placed within a cavity formed inside a mold housing, where resin may be injected to form the memory module. The conductor can also be shaped so as to extend on multiple planes from the connection point on or near the bonding pad to an edge connector residing near one edge only of the memory module. The conductor is thereby connected to the integrated circuit and provides slide-in, releasable coupling to a receptor.

Molded memory module and method of making the module absent a substrate support

Architecture, circuitry, and methods are provided for operating a high speed, volatile programmable logic integrated circuit using back-up non-volatile memory cells configured on an integrated circuit separate from the programmable logic integrated circuit. The lower density non-volatile memory cells can be formed on an integrated circuit using fabrication steps similar to those used to form, e.g., EEPROM devices or, more specifically, flash EEPROM devices. The programmable logic integrated circuit includes high density, volatile memory cells integrated with high speed, low density configurable CMOS-based logic. By using two separate processing technologies on two separate and distinct monolithic substrates, and interconnecting the separate integrated circuits on a singular monolithic substrate, the advantages of non-volatility can be combined with a high speed programmable circuit. The pins extending from the programmable logic device can be mounted in various ways to corresponding receptors on a printed circuit board. The present architecture, circuitry, and method thereby presents a packaged device which inherently has the same characteristics as a single integrated circuit, yet is actually two integrated circuits having the benefits of non-volatility as well as the benefits of higher speed, higher density volatile logic blocks within a programmable logic device or complex programmable logic device.

Architecture, circuitry and method for configuring volatile and/or non-volatile memory for programmable logic applications

An integrated circuit, a programming mechanism and a method are provided for programming test information upon non-volatile storage devices of the integrated circuit. The test information includes a pass/fail outcome arising from one or more test operations to which the integrated circuit is exposed. In addition to or in lieu of the test outcomes, test results of one or more parametric tests at select test operations can be measured from and programmed back into the integrated circuit. Test limits against which the test results can be compared may also be programmed into the integrated circuit. The test outcomes of various test operations, test results of various test parameters and test limits of the same or dissimilar test parameters are stored in separate non-volatile storage locations attributed to the integrated circuit. Those storage locations and, particularly, the bits contained therein are read either before the integrated circuit is packaged, after it is packaged, or after the packaged integrated circuit is shipped to customer. Programming test information as to that particular integrated circuit provides traceability of test operations performed, quality control of integrated circuits shipped, failure analysis of integrated circuits manufactured and, in some instances, lessened overall test time.

Circuitry, apparatus and method for embedding a test status outcome within a circuit being tested

An integrated circuit, a programming mechanism and a method is provided for programming test information upon non-volatile storage devices of the integrated circuit. The test information includes a pass/fail outcome arising from one or more test operations to which the integrated circuit is exposed. In addition to or in lieu of the test outcomes, test results of one or more parametric tests at select test operations can be measured from and programmed back into the integrated circuit. Test limits against which the test results can be compared may also be programmed into the integrated circuit. The test outcomes of various test operations, test results of various test parameters and test limits of the same or dissimilar test parameters are stored in separate non-volatile storage locations attributed to the integrated circuit. Those storage locations and, particularly, the bits contained therein are read either before the integrated circuit is packaged, after it is packaged, or after the packaged integrated circuit is shipped to customer. Programming test information as to that particular integrated circuit provides traceability of test operations performed, quality control of integrated circuits shipped, failure analysis of integrated circuits manufactured and, in some instances, lessened overall test time.

Circuitry, apparatus and method for embedding quantifiable test results within a circuit being tested

An apparatus, method and kit is provided for aligning small, closely spaced leads of an integrated circuit to small, closely spaced test conductors within a test apparatus. The leads can be arranged in various ways, and can extend from dissimilar types of integrated circuit packages. Likewise, the test conductors can be configured from a test socket possibly within a test head. The integrated circuit or DUT is forwarded toward the test conductors by a handler. The kit is used to secure the DUT and align the leads with the test conductors. Alignment can be achieved in either two or three dimensions. According to one embodiment, the kit includes a test socket unique to the DUT having at least one pin, and preferably two pins, extending from the test socket through an insert, also provided with the kit. The insert retains the DUT and the opening within the insert extends over the pin to effectuate two-dimensional alignment. A spacer may also be provided with the kit as an alternative embodiment. The spacer can be affixed to the test socket outside the test conductors. The spacer operates similar to a shim and is designed to abut between the test socket and the insert. A change in the thickness of the spacer will modify the extent by which the leads travel toward and deflect upon respective test conductors. As such, spacer thickness will provide alignment in a third dimension so that optimal electrical contact is achieved between leads and test conductors.

Apparatus, method and kit for adjusting integrated circuit lead

An apparatus, method and kit is provided for aligning small, closely spaced leads of an integrated circuit to small, closely spaced test conductors within a test apparatus. The leads can be arranged in various ways, and can extend from dissimilar types of integrated circuit packages. Likewise, the test conductors can be configured from a test socket possibly within a test head. The integrated circuit or DUT is forwarded toward the test conductors by a handler. The kit is used to secure the DUT and align the leads with the test conductors. Alignment can be achieved in either two or three dimensions. According to one embodiment, the kit includes a test socket unique to the DUT having at least one pin, and preferably two pins, extending from the test socket through an insert, also provided with the kit. T he insert retains the DUT and the opening within the insert extends over the pin to effectuate two-dimensional alignment. A spacer may also be provided with the kit as an alternative embodiment. The spacer can be affixed to the test socket outside the test conductors. The spacer operates similar to a shim and is designed to abut between the test socket and the insert. A change in the thickness of the spacer will modify the spacer thickness will provide alignment in a third dimension so that optimal electrical contact is achieved between leads and test conductors.

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Fremont, CA, United States of America

Khushrav S Chhor