Arm Limited

Khushal Gelda

Andy Wangkun Chen

Yew Keong Chong

Sriram Thyagarajan

Akshay Kumar

Munish Kumar

Vianney Antoine Choserot

Amandeep Kaur

Akash Bangalore Srinivasa

Penaka Phani Goberu

Various implementations described herein are related to a device having first datapath circuitry with input devices that receive data from a number of write ports and provide first data. The device may have second datapath circuitry with logic gates that receive the first data from the input devices and provide the first data based on a read bitline signal. The device may have third datapath circuitry with output devices that receive the first data from the logic gates and provide second data to a number of read ports. Also, the number of read ports is greater than the number of write ports.

Configurable scan chain architecture for multi-port memory

Various implementations described herein are related to a device having multi-port circuit architecture with multiple ports. The multi-port circuit architecture may expand a primary clock into multiple dummy clocks so as to separately track, simulate and report clock power consumption for each port of the multiple ports to a central processing unit.

Multi-port circuit architecture

Various implementations described herein are related to a method for identifying multi-bank memory architecture having multiple banks including a first bank and a second bank. The method may receive a faulty row address having a faulty bank selection bit, and also, the method may select the first bank or the second bank for row redundancy operations based on the faulty bank selection bit.

Row redundancy techniques

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Bengaluru, India

Khushal Gelda