Qualcomm Incorporated

Apple Inc.

Khurram Zaka Malik

Hari Kannan

Rajat Goel

Seong-Ook Jung

Lew G Chua-Eoan

Mohamed Elgebaly

Andrew L Arengo

A circular queue implementing a scheme for prioritized reads is disclosed. In one embodiment, a circular queue (or buffer) includes a number of storage locations each configured to store a data value. A multiplexer tree is coupled between the storage locations and a read port. A priority circuit is configured to generate and provide selection signals to each multiplexer of the multiplexer tree, based on a priority scheme. Based on the states of the selection signals, one of the storage locations is coupled to the read port via the multiplexers of the multiplexer tree.

Lookahead scheme for prioritized reads

A latch circuit. The latch circuit may include an input circuit, a precharge circuit, and a transfer circuit. The precharge circuit may precharge a first node during a first phase of a clock signal. Based on an input signal received at a first logic value, the input signal may drive the first node to a second logic value during the second clock phase. The transfer circuit may include a discharge circuit that is active during an evaluation phase beginning at a delay time subsequent to the clock signal entering the second phase and ending when the clock signal re-enters the first phase. The transfer circuit may also include pull-up and pull-down transistors, one of which may drive a logic value to a second node during the evaluation phase.

Dynamic-to-static converter latch with glitch suppression

The frequency of an oscillating signal generated by a ring oscillator is used to determine the select-to-output delay of standard cell multiplexers. The ring oscillator has no active logic elements other than an odd or even number of standard cell multiplexers. The signal path of the oscillating signal passes through the select input leads of the multiplexers of the ring oscillator. The ring oscillator can be used to characterize how signal propagation delay varies depending on the voltage supplied to the multiplexers. The lowest supply voltage at which a signal can continue to travel through the most critical circuit path of a test circuit can be modeled. In addition, the ring oscillator can be built into operational circuits to monitor timing and signal propagation delay in real time. Real time monitoring of delay enhances the benefits of adaptive voltage scaling, which is used in signal processing circuits in cell phones.

Ring oscillator for determining select-to-output delay of a multiplexer

Techniques for adaptively scaling voltage for a processing core are described. In one scheme, the logic speed and the wire speed for the processing core are characterized, e.g., using a ring oscillator having multiple signal paths composed of different circuit components. A target clock frequency for the processing core is determined, e.g., based on computational requirements for the core. A replicated critical path is formed based on the characterized logic speed and wire speed and the target clock frequency. This replicated critical path emulates the actual critical path in the processing core and may include different types of circuit components such as logic cells with different threshold voltages, dynamic cells, bit line cells, wires, drivers with different threshold voltages and/or fan-outs, and so on. The supply voltage for the processing core and the replicated critical path is adjusted such that both achieve the desired performance.

Adaptive voltage scaling for an electronics device

This disclosure is directed to techniques for reducing erroneous static logic signals when logic signals change relative to a clock signal within a dynamic to static logic converter circuit. Domino logic circuits, for example, utilize dynamic logic signals evaluated relative to a clocking signal. When dynamic logic signals are evaluated, logic signals propagate within logic circuits. Dynamic to static logic converter circuits possess logic signals used to generate static logic signals that change state at well defined points in time relative to a clocking signal used by dynamic logic. Use of a delay for a clocking signal by a latch circuit utilized to capture a dynamic logic signal for conversion to a static logic signal reduces logic level changes in static logic signals during times in which dynamic logic signals may be indeterminate. Use of current limiting circuit elements associated with the latch circuit may further reduce logic level changes during these times in which dynamic logic signals may be indeterminate.

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Santa Clara, CA, United States of America

Khurram Zaka Malik