International Business Machines Corporation

Khuong Huu Pham

Louis Bennie Capps, Jr

Robert Christopher Dixon

Thoi Nguyen

Ronald Xavier Arroyo

Ghadir Robert Gholami

An active circuit for rapidly discharging stored energy in a capacitive system. The circuit is comprised of a variable impedance circuit, a voltage detector, and a time delay circuit. The variable impedance circuit includes a variable impedance output path configured to be connected between a Vcc bus of the capacitive system and ground. The voltage detector circuit includes an input coupled to the Vcc bus and an output connected to an input of the variable impedance circuit. The voltage detector circuit is configured to maintain the variable impedance output path in a high impedance condition while the Vcc voltage remains above a predetermined minimum value. The time delay circuit is coupled to the input of the variable impedance circuit and configured to maintain the variable impedance output path in a low impedance condition for a duration after the voltage of the Vcc bus drops below the predetermined minimum.

Active accelerated discharge of a capacitive system

A bus termination impedance verification circuit. The verification circuit includes a sense circuit comprised of a sense input node and a sense output node. A sense node of the sense circuit is connected to a signal conductor of a bus to detect the termination impedance of the bus. The voltage of the sense output node is indicative of the termination impedance of the bus when the sense circuit input node is activated. The comparator circuit includes a comparator input node and a comparator output node. The comparator input node is connected to the sense circuit output node. The comparator circuit is configured such that the comparator output node is indicative of whether the voltage of the comparator input node is within a specified voltage range. The voltage of the signal conductor, as detected by the sense circuit, will be a function of the impedance of the termination circuits connected to the bus. An excess or shortage of termination circuits connected to the bus will result in a detected control signal voltage that is not within the specified limits.

Circuit for detecting improper bus termination on a SCSI bus

A method and apparatus for driving a battery-backed up clock while a computer system is powered-down. The present invention uses an auxiliary power supply, VAUX, to power a microprocessor bus oscillator. The microprocessor bus oscillator is typically a high frequency, highly accurate oscillator. The microprocessor bus oscillator continues to run while the computer system is powered down, but is connected to a wall outlet. Thus, it can be used to synthesize an accurate time base to drive a battery-backed up clock input. A microcontroller, PAL, or other such circuit can be used to convert the high frequency signal from the microprocessor bus oscillator to a frequency suitable for the battery-backed up clock. Thus, a single oscillator is used to keep time for normal operations. Only when the system is moved, or when main power fails, is a battery backed-up crystal oscillator used to keep time. This minimizes the occurrence of timing errors, due to the system being turned off and back on.

Method and apparatus for driving a battery-backed up clock while a

A method and apparatus of allowing processors of different speeds to be used in a multi-processor system are disclosed. The method and apparatus comprise a programmable array logic (PAL) or field programmable gate array (FPGA) that detects each of the processors maximum speed and selects a speed common to all of the processors as the operating speed of the processors. The method and apparatus also adjust the system clock to match the speed of the processors.

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Austin, TX, United States of America

Khuong Huu Pham