Intel Corporation

Khun Ban

Kingsum Chow

Keqiang Wu

Ying Feng

Shih-Lien L Lu

Christopher B Wilkerson

Zeshan A Chishti

Seth H Pugsley

Shirish Aundhe

Peng-Fei Chuang

Robert L Scott

Zhidong Yu

Sandhya Viswanathan

Generally, this disclosure provides systems, devices, methods and computer readable media for dynamic tuning of multiprocessor and multicore computing systems to improve application performance and scalability. A system may include a number of processing units (CPUs) and profiling circuitry configured to detect the existence of a scalability problem associated with the execution of an application on CPUs and to determine if the scalability problem is associated with an access contention or a resource constraint. The system may also include scheduling circuitry configured to bind the application to a subset of the total number of CPUs if the scalability problem is associated with access contention.

Dynamic tuning of multiprocessor/multicore computing systems

Various embodiments are generally directed to techniques for controlling the use of locks that regulate access to shared resources by concurrently executed portions of code. An apparatus to control locking of a resource includes a processor component, a history analyzer for execution by the processor component to analyze at least one result of a replacement of a lock instruction of a first instance of code with a lock marker to allow the processor component to speculatively execute a second instance of code, and a locking component for execution by the processor component to replace the lock instruction with the lock marker based on analysis of the at least one result, the first and second instances of code to access a resource and the lock instruction to request a lock of access to the resource to the first instance of code. Other embodiments are described and claimed.

Techniques for controlling use of locks

Generally, this disclosure provides systems, devices, methods and computer readable media for estimation of application execution performance variations on a processor, without a priori knowledge of the application. A system may include network traffic data collection circuitry configured to sample a first network traffic statistic, from a network interface circuit associated with the processor, at a first sampling time interval during the application execution. The network traffic data collection circuitry may also be configured to sample a second network traffic statistic from the network interface circuit at a second sampling time interval during the application execution. The system may further include performance analysis circuitry configured to calculate a ratio of the first network traffic statistic to the second network traffic statistic and to estimate the application execution performance variation from the first sampling time interval to the second sampling time interval, wherein the estimation is proportional to the calculated ratio.

Estimation of application performance variation without a priori knowledge of the application

In an embodiment, a processor includes at least one core having one or more execution units, a first cache memory and a first cache control logic. The first cache control logic may be configured to generate a first prefetch request to prefetch first data, where this request is to be aborted if the first data is not present in a second cache memory coupled to the first cache memory. Other embodiments are described and claimed.

Constraining prefetch requests to a processor socket

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Hillsboro, OR, United States of America

Khun Ban