Xilinx, Inc.

Khue Duong

Stephen M Trimberger

Robert O Conn

Sheau-suey Li

Samuel Broydo

Randy T Ong

Bernard J New

Charles R Erickson

Hung-Cheng Hsieh

John E Mahoney

William S Carter

Alok Mehrotra

Ross H Freeman, Deceased

An electrical connection arrangement for a programmable integrated circuit is provided. An electrical device is disposed proximate to a vertical longline which is used for transporting address and data signals. The electrical device includes a vertical address line extending from the device. A horizontally arranged interconnection line is electrically connected to the vertical address line extending from the device. Furthermore, the horizontally arranged interconnection line is programmably connectable to the vertical longline. By electrically hardwire connecting the horizontally arranged interconnection line to the vertical address line extending from the device, only one programmable interconnect point is required to transfer signals from the vertical longline into the electrical device itself. Thus, impedance is reduced, while addressing speed is improved. Also, by adding additional horizontal interconnect lines, the present invention reduces routing barriers.

Dedicated local line interconnect layout

Signal routing resource tiles that can be manipulated as circuit 'cells' in that they can be readily characterized and implemented on a programmable logic device, e.g., a field programmable gate array (FPGA). In one embodiment, vertical placement and horizontal placement routing resource tiles are provided. Routing resources tiles may be selectively added in areas of the programmable logic device determined to be prone to high signal congestion, e.g., the central portions of the array, and along the array perimeter. The additional routing resource tiles simplify routing for complex logic functions and increase utilization of configurable logic blocks (CLBs) forming the array. The tiles can be positioned within the array in any position horizontally or vertically within the CLB array. Specifically, placement can be either in the core of the chip or along the periphery with each tile providing programmable connections to the existing routing resources (e.g., input/output ports) within the CLBs. A corner tile is also provided that permits interconnection between horizontal and vertical tiles. The tiles are modular in nature so the number of tiles provided within an array and their placement are determined based on the array's particular need for routing resources, e.g., an array can have one, two or more tiles associated with a row or column of CLBs in areas of the chip where congestion is typically encountered. Each tile of the present invention can also include a plurality of switch matrices, buffers, or other active gates to facilitate signal routing.

Tile-based modular routing resources for high density programmable logic

A field programmable gate array having independently buffered output lines of a CLB for handling critical path situations. One of the CLB's output ports is coupled to a vertical interconnect line and a horizontal interconnect line. Two separate buffers are used to drive these lines. One buffer drives the horizontal interconnect line, while the other drives the vertical interconnect line. One of these lines is used to conduct the output signal that corresponds to the critical path. The other line is used to conduct the output signal onto other branches that are not part of the critical path. Hence, by using a separate buffer to drive the critical path, it is not loaded with the circuits associated with the non-critical branches.

Multi-buffered configurable logic block output lines in a field

A input/output circuit (IOB) within an integrated circuit (IC) device, the output signal driving circuitry of the input/output device contains a dedicated multiplexer on the output path wherein a first and second output signal can be time multiplexed on a single output pad. The multiplexer can also be configured to perform as a high speed gate to realize AND, OR, XOR, and XNOR functions. Within an input/output circuit of a programmable integrated circuit, the system provides a dedicated multiplexer that can select between one of two output signals for sending over the single output pad of the IC device. In lieu of using a programmable memory cell as the select control for the dedicated multiplexer, the system allows a number of lines, including an output clock signal, to be the select control. By using the output clock as the select control, the data signals can be effectively time multiplexed over a single output pad and referenced by the output clock. This output multiplexer circuit effectively doubles the number of output signals the IC device can provide with a given number of output pads. The dedicated multiplexer when configured as a high speed gate is useful for generating very high speed system level reset or enable signals or any logic function.

Output multiplexer circuit for input/output block

A clock distribution network and mechanisms therein for an integrated circuit (IC) including an edge clock and distribution system for same. The invention includes a deskewed clock distribution network for circuits situated in columns wherein buffering is done in columns less than half of the IC length. The mechanism allows each of at least eight vertical column distribution lines to couple with any horizontal clock supply line of at least eight lines. The horizontal clock supply lines include local interconnect inputs. To increase clock source signals, special lines, Kx lines, are provided that are buffered and traverse directionally in 1/4 IC lengths from the top down, bottom up, and midsection both up and down. Kx lines can be sourced from carry signals, IOBs, interconnects, or from an edge clock and supply to clock lines, longlines, or interconnect lines. Kx lines allow vertical signal displacement, e.g., for clock signals, etc., within the chip. An edge clock is provided that is not deskewed and is directly coupled to an edge clock distribution system along the left and right edges of the IC to supply a clock signal to an entire edge or half of an edge with less delay relative to the deskewed clock. Also, a super fast edge clock is provided for very high speed circuits.

Deskewed clock distribution network with edge clock

An ESD protection circuit combines a split bipolar transistor with a transistor layout which exhibits very high tolerance to ESD events. The split bipolar transistor divides current among many segments and prevents the current hogging which often causes an ESD failure. Several splitting structures are disclosed, each combining a resistor in series with each segment to distribute current evenly. The transistor takes advantage of the snap-back effect to increase current carrying capacity. Layout positions metal contacts away from regions of highest energy dissipation. Layout also allows high currents to be dissipated through ESD protection structures and not through circuit devices such as output drivers or through parasitic bipolar transistors not designed for high current. Sharp changes in electron density are avoided by the use of high-diffusing phosphorus in N-regions implanted to both lightly and heavily doped levels. Critical corners are rounded rather than sharp. Certain P-type channel stop implants are positioned away from nearby N-regions to increase breakdown voltage.

ESD protection circuit

A fast carry-out scheme in a field programmable logic array. The configurable logic blocks (CLBs) are arranged in columns. The carry-out signals are routed from the bottom CLB of a column to the top CLB of that column. The carry-out from the top-most CLB is then multiplexed onto a clock line that is normally used to conduct clocking signals to the CLBs. Instead of conducting clocking signals, the existing clock line is now used to route the carry-out signal onto a vertical longline spanning the entire height of the column. Eventually, the carry-out signal is routed from the longline to its destination CLB of the adjacent column via local interconnect resources.

Fast carry-out scheme in a field programmable gate array

A metal interconnect line for conducting a first signal from a first line segment of a field programmable gate array to a second line segment. The metal interconnect line substantially spans across the width of the field programmable gate array and has at least one bi-directional buffer that separates the metal interconnect line into a plurality of independent segments. Each of these segments can conduct signals independently from the other segments when the bidirectional buffer is in a tristate mode. Alternatively, a single signal may be routed through the entire length of the metal line in one or the other direction, and repowered along the way. One or more of the bi-directional buffers are used to actively drive the signal(s) onto later segments of the metal interconnect line.

Interconnect lines including tri-directional buffer circuits

A mechanism is provided for allowing input/output signal routing along the periphery of a programmable integrated circuit (IC) so that uniform circuit usage across the programmable integrated circuit is allowed in conjunction with predetermined pin assignments. The mechanism includes a plurality of periphery interconnect lines that run along the periphery of a programmable IC. Input/output blocks (IOBs) that are similarly along the periphery of the programmable IC and configurable logic blocks (CLBs) are coupled to the plurality of periphery interconnect lines using a programmable local interconnect structure. Each IOB includes an associated pad and an input/output external pin. Individual segments of the plurality of periphery interconnect lines utilize a bi-directional buffer to buffer a line of the periphery interconnect. Uniform buffered segments of the periphery interconnect are disposed such that for an interconnect of n lines, each line of the periphery interconnect is buffered at least once every n segments. In operation, a CLB located away from the periphery of the IC can output a signal over the local interconnect, onto the plurality of periphery interconnect lines, onto another local interconnect, into an IOB and over its external pin. To input a signal, the path is reversed. The pin and the CLB do not need to be adjacent.

Periphery input/output interconnect structure

A programmable single buffered six transistor switch box is provided. A six transistor switch box acts as a programmable junction between four intersecting lines. The switch box allows any two of the lines to be programmably interconnected to form a signal channel. Alternatively, two sets of the four lines can also be programmably interconnected so that two signal channels are formed. The present invention modifies the known six transistor switch box so that one line output from the switch box can be programmably buffered. By buffering the output signal, delay introduced by resistance and capacitance of the transistors switch box is significantly reduced. For short line lengths, the buffer delay can be greater than the delay associated with the resistance and capacitance of the transistors of the switch box. In these cases, the output is not buffered and the buffer is programmably bypassed. Although there are four possible outputs that can be programmably selected in the present invention switch box, the present invention advantageously utilizes a single buffer resource to perform output buffering. A multiplexer circuit and demultiplexer circuit configuration is used to perform the proper routing.

Programmable single buffered six pass transistor configuration

A input/output circuit (IOB) within an integrated circuit (IC) device, the output signal driving circuitry of the input/output device contains a dedicated multiplexer on the output path wherein a first and second output signal can be time multiplexed on a single output pad. The multiplexer can also be configured to perform as a high speed gate to realize AND, OR, XOR, and XNOR functions. Within an input/output circuit of a programmable integrated circuit, the system provides a dedicated multiplexer that can select between one of two output signals for sending over the single output pad of the IC device. In lieu of using a programmable memory cell as the select control for the dedicated multiplexer, the system allows a number of lines, including an output clock signal, to be the select control. By using the output clock as the select control, the data signals can be effectively time multiplexed over a single output pad and referenced by the output clock. This effectively doubles the number of output signals the IC device can provide with a given number of pads. The dedicated multiplexer when configured as a high speed gate is useful for generating very high speed system level reset or enable signals or any logic function.

Output multiplexer within input/output circuit for time multiplexing and

A configurable multi-directional buffer circuit for a programmable integrated circuit. The novel buffer circuit is a configurable multi-directional buffer circuit having one pair of inverters and having a first input/output line and a second input/output line and a third input line multiplexed with the first input/output line. The novel buffer circuit is configurable to allow a signal from the first input/output line to be driven over the second input/output line or configurable to allow a signal from the second input/output line to be driven over the first input/output line. The novel buffer circuit also allows a signal over the third input line to be driven over the second input/output line. In either case, only a single pair of inverter circuits are used. In an alternate embodiment, the novel buffer allows signal over a fourth input line to be driven over the first input/output line. The novel buffer is configurable to realize any of the above configurations using programmable memory cells and therefore is well suited for application within a programmable integrated circuit. Since the novel buffer utilizes only a single pair of inverters to provide the buffering, in any configuration, it does not contain unused driver circuitry when configured. Therefore, the novel buffer advantageously consumes a relatively small amount of substrate area.

Tri-directional buffer

A structure especially useful in a configurable logic array includes a plurality of conductive interconnect lines located along the perimeter of a logic array chip. Lines running from exterior pins or pads can be used by a programmable interconnect circuit to control signals applied to these interconnect lines. In particular, both the signal and the complement of the signal can be used by the programmable interconnect to control application of a supply voltage to an interconnect line. A second supply voltage is applied through a resistor to the interconnect line with the result that the interconnect line will carry a logical signal representing a logical function, for example AND, of a selected set of input signals or their complements. Lines running from points interior to the configurable logic array chip may also contribute to the signal generated on an interconnect line. In one embodiment, bidirectional programmable interconnect circuits allow the input pins to function as either input or output pins. An application of the decoder circuit is described for use with a latch as a data/address demultiplexer.

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San Jose, CA, United States of America

Khue Duong