International Business Machines Corporation

Apple Inc.

Khubaib Khubaib

Vijayalakshmi Srinivasan

Stephan G Meier

Tyler J Huberty

Moinuddin Khalil Ahmed Qureshi

In an embodiment, a system may include multiple processors and a cache coupled to the processors. Each processor includes a data cache and a prefetch circuit that may be configured to generate prefetch requests. Each processor may also generate memory operations responsive to cache misses in the data cache. Each processor may transmit the prefetch requests and memory operations to the cache. The cache may queue the memory operations and prefetch requests, and may be configured to detect, on a per-processor basis, occupancy in the queue of memory requests and low confidence prefetch requests from the processor. The cache may determine if the per-processor occupancies exceed one or more thresholds, and may generate a throttle control to the processors responsive to the occupancies. In an embodiment, the cache may generate the throttle control responsive to a history of the last N samples of the occupancies.

Prefetch throttling in a multi-core system

Disclosed is an apparatus to reduce broadcasts in multiprocessors including a plurality of processors; a plurality of memory caches associated with the processors; a plurality of translation lookaside buffers (TLBs) associated with the processors; and a physical memory shared with the processors memory caches and TLBs; wherein each TLB includes a plurality of entries for translation of a page of addresses from virtual memory to physical memory, each TLB entry having page characterization information indicating whether the page is private to one processor or shared with more than one processor. Also disclosed is a computer program product and method to reduce broadcasts in multiprocessors.

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Austin, TX, United States of America

Khubaib Khubaib