Motorola Corporation

Freescale Semiconductor,inc.

Khoi Van Dinh

Alexander Hoefler

Clinton Thomas Glover

Matthew Russell Nixon

Robert Arthur Jensen

Matthew B Rutledge

A device for reducing the effects of leakage current within electronic devices is disclosed. In one form, a high voltage driver includes a high voltage source coupled to at least one high voltage transistor and a leakage offset module coupled to at least a portion of one of the high voltage transistors. The leakage offset module includes a diode connected MOS device operable to generate an offset voltage and an MOS shunting device coupled in a parallel with the diode connected MOS device. During operation, the diode connected MOS device generates an offset voltage based on a sub-threshold leakage associated with using the high voltage source and the MOS shorting device is operable to short the diode connected MOS device when sub-threshold leakage current is relatively low.

Device for reducing sub-threshold leakage current within a high voltage driver

In a data processing system, a memory control unit (22) provides a control register bit field (60), logic, and a state machine (62) which facilitate a programmable number of clocks for an initial access to an on-chip memory (20). Specifically, the memory control unit (22) allows an external user to modify memory control signals to provide consistent access times across different frequencies of the system clock and allows memory control signals to be modified to optimize access time dynamically. Also, programmable control of the control signals to the memory (20) allows the memory to operate at system clock frequencies which are higher than expected.

Method and apparatus for selectively programming access time in a data

Clock frequency and number of stages of a charge pump for nonvolatile memories are automatically adjusted to compensate for lower efficiency due to lower power supply, higher temperature, or weaker process. A low voltage detector will cause the charge pump to increase the charge pump's clock frequency and number of stages when a low voltage is detected, making the charge pump's capability constant over a voltage range. A counter timing programming/erasing time will cause the charge pump clock frequency and number of stages to increase when the programming/erasing time exceeds certain thresholds. This boosts the charge pump's drivability for a weaker process, higher temperature, or aged cells.

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Austin, TX, United States of America

Khoi Van Dinh