Extreme Networks, Inc.

Khoi D Vu

Erik R Swenson

Brian C Edem

Siddharth Khattar

Thuan D Nguyen

James Robert Bauder

Kevin S Fatherree

Kathleen E Cimino

A memory array comprises N+1 memory elements. N memory elements store data and one or more error check bits respectively derived from the stored data. A separate N+1 memory element stores parity bits generated from the data stored in the N memory elements. These parity bits are stored in. To recover from data errors, data in each N memory element are first checked using their respective error check bits. If faulty data are detected in one of the N memory elements, an exclusive-or operation is performed involving data in the remaining N&#x2212;1 memory elements and parity bits in the N+1 memory element. This recovers the faulty data in the one memory element.

Memory array error correction

A method of and system for transferring overhead data from a sender to a receiver over a serial interface is provided. The overhead data is transferred over one or more data lines of the interface during one or more time periods in which excess bandwidth is available on the one or more data lines or while the transfer of the overhead data does not substantially impede the throughput of the payload transfer.

Method of and system for transferring overhead data over a serial interface

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Valley Village, CA, United States of America

Khoi D Vu