Texas Instruments Corporation

3 Com Corporation

Khodor S Elnashar

Jay T Cantrell

Clarence D Lewis

William Alan Saperstein

Brian T Deng

Robert C Suffern

Stephen R Tomassetti

Philip A Roden

Ronald Joseph Sullivan

Alan T Wetzel

Brett Walter Chaveriat

Steve K Tsang

Mahmoud M Yazdani

Rich A Rochelle

Qinghua Chen

Kishore Mishra

A Duty cycle optimized prescaler (,) optimizes the clock duty cycle as close as possible to fifty percent. This is achieved by employing two count by two counters (,), one (,)to count negative edges of the clock pulse, and one (,)to count positive edges of the clock pulse. Each counter (,) output is connected to a comparator (,) which compares each counter output (,)to a prescaler setting (,). The comparators (,) outputs are input to an OR gate (,), the output of which, when, a logic 1, resets the counters(,) and toggles a flip-flop circuit (,) providing a clock output signal.

Duty cycle optimized prescaler

A power reduction system for a UART system having a controllable oscillator for producing free-running clock signals. A controlled clock synchronizer having an output terminal is coupled to the oscillator and responsive to both a first control signal thereto and application of the free-running clock signals thereto to provide synchronized pulses and is responsive to both a second control signal different from the first control signal thereto and application of the free-running clock signals thereto to cease production of the synchronized pulses at the output terminal. A UART core controls the oscillator and the clock synchronizer and is operated under control of clock signals from the clock synchronizer. The controllable oscillator includes an inverter having a feedback circuit thereacross including a switch responsive to the third control signal to cause the oscillator to cease oscillation. The synchronizer includes a bistable circuit responsive to the first and second control signals and a gate responsive to the bistable circuit and the clock signals for controlling the status of the synchronized pulses at the output terminal.

Power reduction for UART applications in standby mode

A processor on an add-on card that arbitrates demand on a memory unit on the add-on card. The processor and memory unit are used for the underlying functionality of the add-on card. The processor determines an appropriate time to allow interface operations to the memory unit when the memory unit is not already being accessed for the underlying functionality of the card. By using the processor and memory unit on the add-on card for interface operations to the host computer, the add-on interface circuitry on the add-on card can be minimized and simplified.

System for arbitrating demand on memory during configuration of a

A dual bus controller includes a system bus control module connected to a local bus control module. An optional filter is also connected to the system bus control module. A plurality of programmable status registers for the local bus is connected to the local bus control module and a time dependent reset circuit is connected to both the system bus control module and the local bus control module. The dual bus controller allows simultaneous, autonomous activity with both the local bus and the system bus via the local bus and system bus control modules. The unique interaction between the local bus and system bus control modules also allow both the local bus and system bus to interact with the dual bus controller operating as a slave without any imposed speed limitations by actively resolving bus collisions and 'live-lock' conditions.

Integrated dual bus controller

An embodiment of the present invention is a digital circuit (block 12 of FIG. 1) for interfacing between a first bus (10), which can operate synchronously or asynchronously, and a second bus (14), which can operate synchronously or asynchronously, the digital circuit comprising: compelled data decoders (40 and 50) connected to the first bus for receiving compelled data and decoding the compelled data; packet data decoders (52 and 45) connected to the first bus for receiving packet data and decoding the packet data; a digital storage device (28), preferably a FIFO comprising a plurality of write banks and a plurality of read banks or a FIFO comprising a plurality of dual-ported RAMs, having an input selectively connected to the compelled data decoders, the packet data decoders, and the second bus (via lines 44) for storing the decoded data and data from the second bus, the digital storage device additionally includes an output connected to the second bus (via lines 42) for outputting the stored decoded data to the second bus; compelled data encoders connected to the output of the digital storage device for encoding the stored data received from the second bus and outputting the encoded data to the first bus; and packet data encoders (34 and 36) connected to the output of the digital storage device for encoding the stored data received from the second bus and outputting the encoded data to the first bus. Preferably, multiple bits of data are progressively written into each write bank of the digital storage device within a clock cycle whereby the data is stored at a rate higher than the FIFO could store with a single bank. The first bus can operate synchronously or asynchronously and the second bus can also operate synchronously or asynchronously. The first and second buses can operate at different clock rates and have different data widths.

Programmable dual port data unit for interfacing between multiple buses

An improved data sampling system for sampling data transmission in a computer system includes a reference clock, a delay locked loop circuit, a packet enable circuit, a delayed selector control circuit, a sample selector, and a sample circuit. The devices may be constructed on a single semiconductor substrate and may be connected to a bus structure having a microcomputer and a plurality of boards coupled to it. The delay locked loop circuit generates accurate delayed clock signals based on the reference clock. A positive edge synchronizer circuit, within the delay locked loop, serves as a programmable phase adjust for the sampling system. The positive edge synchronizer ensures proper phase relationship between the chosen delayed clock signal and the incoming data across semiconductor process variations. Packet enable circuit informs the delayed control circuit and the sample circuit when a start bit or stop bit is initiated in a data packet and enables those circuit blocks accordingly. The delayed selector control circuit uses the delayed clock signals to detect a start bit on a data signal. The delayed selector control circuit employs the data signal, delayed appropriately, as a metastability hardener to eliminate potential metastability problems associated with coincident data and delay locked loop signal waveforms. The sample selector, in response to detection of the start bit by the delayed selector control circuit, selects two sampling signals from the delay locked loop circuit for even bit and odd bit sampling in the sample circuit.

Packet data recovery system

A glitch filter identifies and eliminates positive edge and negative edge glitches without utilizing a high frequency sampling clock. The glitch filter comprises a programmable delay buffer string, two multiple input AND gates and a latch. The buffer string provides a plurality of incrementally delayed signals and utilizes them as signal samples thus simulating a high frequency sampling clock. The two multiple input AND gates serve to eliminate positive or negative edge glitches. The latch outputs the accurate filtered data without any positive or negative edge glitches.

Programmable glitch filter

A reference time signal generation system 10 is provided which comprises a phase lock loop circuit 12 which generates a reference voltage V.sub.m. The phase lock loop circuit 12 comprises first and second divider circuits 14 and 18 coupled to the input of a phase comparator 16. The output of the phase comparator 16 is coupled to a loop filter 20 which generates a DC representation of the phase differential of the inputs of the phase comparator 16. The output of the loop filter 20 is input into a bias generator 26. The output of the bias generator 26 is coupled to the input of a voltage controlled oscillator 28 which has its output coupled to the input of second divider circuit 18. The reference voltage signal V.sub.m is taken from the output of the bias generator 26 and is transmitted to remote timing elements 32, 34 and 36 where it may be used to create reference timing signals which will accurately track the reference clock signal input into phase lock loop circuit 12.

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Richardson, TX, United States of America

Khodor S Elnashar