Chartered Semiconductor Manufacturing Ltd (corporation)

Globalfoundries Singapore Pte. Ltd.

Kho Liep Chok

Liang Choo Hsia

Fan Zhang

Tae Jong Lee

Xiaomei Bu

Juan Boon Tan

Alex See

Jia Zhen Zheng

Wei Lu

Bei Chao Zhang

Wuping Liu

Marvin De-Dui Liao

Huey Ming Chong

Yih-Shung Lin

Luona Goh

Yee Mei Foong

Xian Bin Wang

Chian Yuh Sin

Cheng-Cheh Tan

Meng Luo

Example embodiments of a structure and method for forming a copper interconnect having a doped region near a top surface. The doped region has implanted alloying elements that block grain boundaries and reduce stress and electro migration. In a first example embodiment, the barrier layer is left over the inter metal dielectric layer during the alloying element implant. The barrier layer is later removed with a planarization process. In a second example embodiment the barrier layer is removed before the alloying element implant and a hard mask blocks the alloying element from being implanted in the inter metal dielectric layer.

Grain boundary blocking for stress migration and electromigration improvement in CU interconnects

In accordance with the objectives of the invention a new design and method for the implementation thereof is provided in the form of an 'oxide ring'. A conventional die is provided with a guard ring or sealing ring, which surrounds and isolates the active surface area of an individual semiconductor die. The 'oxide ring' of the invention surrounds the guard ring or sealing ring and forms in this manner a mechanical stress release buffer between the sawing paths of the die and the active surface area of the singulated individual semiconductor die.

Method of fabrication of a die oxide ring

A method of manufacturing an integrated circuit provides a substrate having a semiconductor device, and includes forming an intermetal dielectric layer over the substrate and the semiconductor device. A metal wire is formed above the semiconductor device and in contact therewith and a passivation layer is formed over the intermetal dielectric layer. A bond pad is formed connected to the metal wire. A protective moat, with sidewall passivation layer, is formed through the passivation layer and the intermetal dielectric layer, and is located between the metal wire and an outside edge of the integrated circuit.

Integrated circuit with protective moat

A method of forming via plugs in a semiconductor device, comprising the following steps. A semiconductor structure having an upper first oxide layer and at least two metal lines formed on the upper oxide layer are provided. The metal lines are spaced apart a predetermined distance and each having a lower barrier layer, a middle layer, and an upper etch stop layer. A second oxide layer is deposited over the first oxide layer and the pair of metal lines. An etch barrier layer is formed over the second oxide layer. The structure is planarized to form openings in the etch barrier layer over the metal lines. A third oxide layer is deposited and patterned over the planarized structure to form via openings through the etch barrier layer openings to the upper etch stop layers on the metal lines. Metal via plugs are formed in the via openings.

Process for borderless stop in tin via formation

A method for forming a dielectric layer within a microelectronics fabrication. There is first provided a substrate. There is then formed over the substrate a polysilicon resistor. There is then formed over the polysilicon resistor a first dielectric layer formed of a silicon nitride dielectric material deposited employing a plasma enhanced chemical vapor deposition (PECVD) method other than a high density plasma chemical vapor deposition (HDP-CVD) method. Finally, there is then formed over the first dielectric layer a second dielectric layer deposited employing a high density plasma chemical vapor deposition (HDP-CVD) method, where first dielectric layer attenuates a decrease in resistance of the polysilicon resistor incident to forming the second dielectric layer over the first dielectric layer.

Plasma enhanced chemical vapor deposited (PECVD) silicon nitride barrier

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Singapore, Singapore

Kho Liep Chok