Broadcom Corporation

Avago Technologies General IP (Singapore) Pte. Ltd.

Khim Leng Low

Akira Ito

Todd Lee Brooks

Agnes Woo

John S Walley

Yasantha N Rajakarunanayake

Angel Arturo Polo

Hua Beng Chan

David Ho

David Seng Poh Ho

Ming Yu Lin

Wee Teck Lee

Tak Ying Wong

Domitille Odile Emmeline Esnard-Domerego

Chi-Ming Hsiao

Lee Song Cher

Power distribution circuitry to improve wireless power distribution and facilitate wireless power transfer (WPT) operations in a wireless communication device under a variety of operating conditions. In various exemplary embodiments of the disclosure, the power distribution circuitry operates to provide a wireless power (WP) supply voltage to wireless communication circuitry of the device in order enable a WPT connection procedure under certain low power conditions. Such conditions might include a power off mode, a sleep mode, and dead/low battery operating conditions wherein the available battery supply voltage is less than a threshold voltage required to enable device components. The power distribution circuitry may switch the supply voltage of the wireless communication circuitry to another available supply voltage source after the WPT connection procedure is completed and wireless power is being received by the wireless communication device.

Selective power distribution during wireless charging

A switching regulator automatically operates in pulse width modulation ('PWM') mode for high load currents and in burst mode for low load currents. The switching regulator includes a pair of switches to provide a regulated current to a load. The switching regulator further includes a multi-input comparator. A first input of the comparator is coupled to an output of the pair of switches. A second input of the comparator is coupled to a filtered version of the output and a third input is coupled to a reference waveform. The first, second and third inputs of the comparator form a combined input signal to the comparator. An output signal of the comparator is generated by comparing the combined input signal to a threshold of the comparator. The output signal determines a switching frequency of the pair of switches such that the switching frequency is automatically reduced when the load is decreased.

PWM/burst mode switching regulator with automatic mode change

The present invention relates to systems and methods for programming a memory cell. More specifically, the present invention relates to a controlled application of current to a memory cell over a controlled time period. The invention utilizes a current mirror configuration having a first transistor and a second transistor, wherein the second transistor is coupled to the memory cell. Programming of the memory cell includes applying a voltage to the first transistor, whereby a first current is generated in the first transistor. A gate of the second transistor is coupled to the first transistor, whereby a second current is generated in the second transistor. The second current is proportional to the first current. The second current is provided to the memory cell, whereby the second current programs the memory cell.

System and method for programming a memory cell

The present invention is directed to systems for evaluating one-time programmable memory cells. A threshold current is applied to a resistive circuit, thereby generating a threshold voltage. A read current is applied to a first memory cell, thereby generating a memory cell voltage. The memory cell voltage is compared to the threshold voltage, thereby determining the state of the memory cell. In a further embodiment of the invention, a second threshold voltage is generated and compared the memory cell voltage, thereby verifying the state of the memory cell. The threshold current is optionally a substantial replica of said read current. The threshold current is optionally a proportional substantial replica of said read current. In an embodiment, the resistive circuit includes a second memory cell, which can be programmed or unprogrammed. The second memory cell is optionally arranged to average the memory cell resistance.

Systems for programmable memory using silicided poly-silicon fuses

A current mode logic (CML) flip flop includes a first CML latch and a second CML latch. A plurality of pull-up switches are responsive to a reset signal. Outputs of the first and second CML latches are pulled up to a supply voltage through the pull-up switches. The first CML latch includes a first pull-up isolation switch driven by the reset signal for resetting the latch.

Circuit for asynchronous reset in current mode logic circuits

The present invention is directed to methods and systems for evaluating one-time programmable memory cells. A threshold current is applied to a resistive circuit, thereby generating a threshold voltage. A read current is applied to a first memory cell, thereby generating a memory cell voltage. The memory cell voltage is compared to the threshold voltage, thereby determining the state of the memory cell. In a further embodiment of the invention, a second threshold voltage is generated and compared the memory cell voltage, thereby verifying the state of the memory cell. The threshold current is optionally a substantial replica of said read current. The threshold current is optionally a proportional substantial replica of said read current. In an embodiment, the resistive circuit includes a second memory cell, which can be programmed or unprogrammed. The second memory cell is optionally arranged to average the memory cell resistance.

Methods and systems for programmable memory using silicided poly-silicon fuses

Growing community of inventors

Singapore, Singapore

Khim Leng Low