Globalfoundries Singapore Pte. Ltd.

Chartered Semiconductor Manufacturing Ltd (corporation)

International Business Machines Corporation

Khee Yong Lim

Kiok Boone Elgin Quek

Wenhe Lin

John Leonard Sudijono

Liang Choo Hsia

Xinshu Cai

Yong Meng Lee

Chung Woh Lai

Young Way Teh

Hui Peng Koh

Kian Ming Tan

Wee Leng Tan

Shyue Seng Tan

Victor Chan

Elgin Kiok Boone Quek

Chia Ching Yeo

Zufa Zhang

Eng Huat Toh

Juan Boon Tan

Elgin Kiok Quek

Fan Zhang

Eng Hua Lim

Jamin F Fen

Sandipta Roy

Ming-Tsang Tsai

Jae Han Cha

Donald Ray Disney

Wanbing Yi

Bin Liu

Yung Fu Chong

Lanxiang Wang

Chim Seng Seet

Shaoqiang Zhang

Yongshun Sun

Lulu Peng

Lawrence Selvaraj Susai

Xinfu Liu

Laiqiang Luo

Jiacheng Lei

Zhiqiang Teo

Fangxin Deng

Danny PakChum Shum

James Jerry Joseph

Quek Kiok Boone Elgin

Cancan Wu

Jing Hua Michelle Tng

Zhang Zufa

Ming Tsang Tsai

Rajesh Nair

Yongtian Hou

Thanh Hoa Phung

Xiao Mei Elaine Low

Structures for an avalanche photodetector and methods of forming a structure for an avalanche photodetector. The structure comprises a substrate having a first conductivity type, a first semiconductor layer that defines an absorption region of the avalanche photodetector, a dielectric layer between the first semiconductor layer and the substrate, a charge control region comprising a semiconductor material having a second conductivity type opposite to the first conductivity type and a different bandgap from the first semiconductor layer, and a second semiconductor layer that extends through the dielectric layer from the charge control region to the substrate. The second semiconductor layer defines a multiplication region of the avalanche photodetector.

Avalanche photodetectors with a combined lateral and vertical arrangement

Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. The structure comprises a semiconductor layer, a first raised source/drain region on the semiconductor layer, a second raised source/drain region on the semiconductor layer, a gate electrode laterally between the first raised source/drain region and the second raised source/drain region, a first airgap laterally between the first raised source/drain region and the gate electrode, and a second airgap laterally between the second raised source/drain region and the gate electrode. The gate electrode includes a first section and a second section between the first section and the semiconductor layer, the first section of the gate electrode has a first width, the second section of the gate electrode has a second width, and the first width is greater than the second width.

Field-effect transistors with airgap spacers

A structure includes a photodetector including alternating p-type semiconductor layers and n-type semiconductor layers in contact with each other in a stack. Each semiconductor layer includes an extension extending beyond an end of an adjacent semiconductor layer of the alternating p-type semiconductor layers and n-type semiconductor layers. The extensions provide an area for operative coupling to a contact. The extensions can be arranged in a cascading, staircase arrangement, or may extend from n-type semiconductor layers on one side of the stack and from p-type semiconductor layers on another side of the stack. The photodetector can be on a substrate in a first region, and a complementary metal-oxide semiconductor (CMOS) device may be on the substrate on a second region separated from the first region by a trench isolation. The photodetector is capable of detecting and converting near-infrared (NIR) light, e.g., having wavelengths of greater than 0.75 micrometers.

Multi-semiconductor layer photodetector and related method

A diode device may be provided, including a semiconductor substrate including a well region arranged therein, a first doped region and a second doped region arranged within the well region, a first contact region arranged within the first doped region, and an isolation structure arranged within the first doped region, where an oxide layer may line a surface of the isolation structure. The first doped region and the first contact region may have a first conductivity type, and the well region and the second doped region may have a second conductivity type different from the first conductivity type. A doping concentration of the first contact region may be higher than a doping concentration of the first doped region, and a part of the first doped region may be arranged between the first contact region and the well region.

Diode devices and methods of forming diode devices

According to various embodiments, a memory cell may include a substrate of a first conductivity type, the substrate having first and second regions of a second conductivity type spaced apart and defining a channel region therebetween. The memory cell may further include a word line arranged over a portion of the channel region nearer to the first region, an erase gate arranged over the second region, a floating gate arranged over another portion of the channel region nearer to the second region and between the word line and the erase gate, and a coupling gate arranged over a top end of the floating gate. The floating gate includes the top end, a bottom end, a first side extending from the top end to the bottom end and facing the erase gate, and a second side extending from the top end to the bottom end and facing the word line. A first lateral distance between the bottom end of the floating gate and the erase gate may be larger than a second lateral distance between the top end of the floating gate and the erase gate.

Memory cells and methods of forming a memory cell

A transistor device may be provided, including a substrate; a buffer layer arranged over the substrate; a source terminal, a drain terminal, and a gate terminal arranged over the buffer layer; a barrier layer arranged over the buffer layer; and a passivation layer arranged over the barrier layer. The gate terminal may be arranged laterally between the source terminal and the drain terminal, the barrier layer may include a recess laterally between the gate terminal and the drain terminal, a part of the gate terminal may be arranged over the passivation layer and the passivation layer may extend into the recess of the barrier layer.

Transistor devices and methods of forming transistor devices

According to various embodiments, there is provided a diode device including a semiconductor substrate of a first conductivity type, a first semiconductor region formed within the semiconductor substrate, an epitaxial region of the first conductivity type, and a second semiconductor region of a second conductivity type different from the first conductivity type. The first semiconductor region includes a chalcogen. The epitaxial region is formed over the first semiconductor region. The second semiconductor region is formed over the epitaxial region.

Diode devices and methods of forming a diode device

An image sensor pixel comprises a semiconductor substrate and a gate having a dielectric layer with a first section and a second section over the semiconductor substrate. The first section of the dielectric layer is thinner than the second section. A photodiode is disposed substantially beneath the gate. A gate well region is disposed beneath the gate and overlying the photodiode. A first doped semiconductor region separates the gate well region from a second doped semiconductor region. The second doped semiconductor region is in the semiconductor substrate and is adjacent to the gate.

Image sensor with reduced capacitance transfer gate

A memory device may include a substrate, a first gate structure, a mask and a second gate structure. The substrate may include a source region and a drain region at least partially arranged within the substrate, and a channel region arranged between the source region and the drain region. The first gate structure may be at least partially arranged over the channel region, and may include a top surface that may be substantially flat. The mask may be at least partially arranged over the top surface of the first gate structure. The second gate structure may be at least partially arranged over the mask and at least partially arranged adjacent to the first gate structure.

Memory device and a method for forming the memory device

A sensor device may include a substrate, first and second source regions, first and second drain regions, first and second channel regions, and first and second gate structures disposed over the first and second channel regions, respectively. The source regions and drain regions may be at least partially disposed within the substrate. The first and second source regions may have first and second source resistances, respectively, and the second source resistance may be higher than the first source resistance. The first gate structure may receive a solution, and a change in pH in the solution may cause a change in a first current flow through the first channel region. In turn, the second current flow through the second channel region may change to compensate for the change in the first current flow to maintain a constant current flow through the sensor device.

Sensor device and a method for forming the sensor device

A semiconductor device having a substrate with at least one photo-detecting region and at least one bond pad is provided. A first passivation layer is deposited over the substrate and over step portions at the edges of the bond pad and a trench having sidewalls and a bottom surface is formed in the substrate. A light shielding layer is deposited over the first passivation layer and covering the trench sidewalls. The light shielding layer has end portions at the photo-detecting region, at step portions at the edges of the bond pad and at the bottom surface of the trench. A second passivation layer is deposited over the light shielding layer. A third passivation layer is deposited over the end portions of the light shielding layer at the photo-detecting region and at the step portions at edges of the bond pad.

Selective shielding of ambient light at chip level

The present disclosure relates to semiconductor structures and, more particularly, to extended drain MOSFET structures with a dual oxide thickness and methods of manufacture. The structure includes an extended drain metal oxide semiconductor transistor (EDMOS) comprising a gate structure with a dual oxide scheme.

Extended drain MOSFETs (EDMOS)

Methods for producing FETs with negative capacitance and the resulting device are disclosed. Embodiments include forming a gate stack over a semiconductor substrate by: forming a gate oxide over the semiconductor substrate; forming a first metal gate electrode over the gate oxide; forming a dummy gate over the metal gate electrode; and forming sidewall spacers on first and second sides of the gate stack; forming an ILD over the substrate and gate stack; removing the dummy gate and at least a portion of sidewall spacers to form an opening; forming a ferro-electric (FE) layer in the opening; and forming a second metal gate electrode over the FE layer.

Method to fabricate capacitance-matching FET and related device

A method of forming a device including a SPAD detector and a BSI visible light sensor positioned on different planes, the device exhibiting improved resolution and pixel density are provided. Embodiments include a photodiode for detecting visible light; and a SPAD detector for detecting IR radiation, wherein the photodiode and the SPAD detector are on different planes.

Image sensor with stacked SPAD and method for producing the same

The disclosure is related to MV transistors with reduced gate induced drain leakage (GIDL) and impact ionization. The reduced GILD and impact ionization are achieved without increasing device pitch of the MV transistor. A low voltage (LV) device region and a medium voltage (MV) device region are disposed on the substrate. Non-extended spacers are disposed on the sidewalls of the LV gate in the LV device region; extended L shaped spacers are disposed on the sidewalls of the MV gate in the MV device region. The non-extended spacers and extended L shape spacers are patterned simultaneously. Extended L shaped spacers displace the MV heavily doped (HD) regions a greater distance from at least one sidewall of the MV gate to reduce the GIDL and impact ionization of the MV transistor.

Transistor with source-drain silicide pullback

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Singapore, Singapore

Khee Yong Lim