Intel Corporation

Khee Wooi Lee

Darren L Abramson

Mikal Hunsaker

William A Stevens, Jr

Kie Woon Lim

Ioannis T Schoinas

Gautham N Chinya

Michael T Klinglesmith

Jose Niell

Michael Berger

Raul N Gutierrez

Mukesh Kataria

Chang Yong Kang

Robert De Gruijl

Josh Triplett

Kah Meng Yeem

Robert DeGruijl

E-Liang Chew

Mikal C Hunsaker

Raul Gutierrez

A system-on-chip (SoC) includes a host CPU on a CPU fabric, the host CPU including multiple processor cores, each associated with multiple security attributes. The SoC includes a secure asset on a network-on-chip and a security co-processor. The security co-processor includes circuitry to detect requests from the processor cores targeting the secure asset and security function processing requests, to determine, based on associated security attributes, whether the core or function is authorized to access the secure asset, to allow the request to be issued, if the core or function is so authorized, and to prevent its issuance, if not. The determination may be dependent on a signal from the CPU fabric indicating whether the host CPU can modify its security attributes or they are locked down. The security co-processor may have the highest security level and may be the only master on the SoC that can access the secure asset.

Migration of trusted security attributes to a security engine co-processor

In one embodiment, a system includes: a first root space associated with a first root space identifier and including at least one first host processor and a first agent, the at least one first host processor and the first agent associated with the first root space identifier; a second root space associated with a second root space identifier and including at least one second host processor and a second agent, the at least one second host processor and the second agent associated with the second root space identifier; and a shared fabric to couple the first root space and the second root space, the shared fabric to route a transaction to the first root space or the second root space based at least in part on a root space field of the transaction. Other embodiments are described and claimed.

Providing multiple roots in a semiconductor device

A method and apparatus is disclosed herein for performing write-only inter processor reset synchronization. In one embodiment, the processing unit comprises: a communication unit to transmit information to the second processing unit; memory to store reset synchronization information and message information; and processing logic to perform write-only reset synchronization between itself and the second processing unit based on bit indications set in the memory.

Method and apparatus for write-only inter-processor reset synchronization

In one embodiment, the present invention includes a method for receiving requests from requestors in an arbiter, detecting that none of the requestors have a qualified request for at least one cycle of an arbitration round, and preventing a grant count reload of grant counters associated with the when at least one of the requestors has available grants for the arbitration round. Other embodiments are described and claimed.

Providing adaptive bandwidth allocation for a fixed priority arbiter

Techniques for maintaining an order of transactions in a multi-bus computer architecture. In an embodiment, an arbitrator receives access requests from a plurality of requestors, each access request requesting a respective access to a bus. Based on an arbitration between the access requests&#x2014;e.g. between those requestors providing the access requests&#x2014;the arbitrator may generate a grant message which triggers a carrying of a first message on the first bus. In certain embodiments, the grant message further triggers another carrying of the first message on the second bus.

Method, apparatus and system for maintaining transaction coherecy in a multiple data bus platform

Techniques for generating access information indicating a least recently used (LRU) memory region in a set of memory regions. In an embodiment, data is stored in an entry of an LRU tracking list (LTL) based on a touch message indicating when a memory group has been touched&#x2014;e.g. read from, written to and/or associated with a memory region. The data stored in an LTL entry may include an identifier of a memory group and/or validity data specifying whether that LTL entry stores a set of default data. In another embodiment, access information may be generated based on the memory group identifier and the validity data.

Method, apparatus and system for generating access information from an LRU tracking list

Method and apparatus for arbitrating prioritized cycle streams in a manner that prevents starvation. High priority and low priority arbitration pools are employed for arbitrating multiple input cycle streams. Each cycle stream contains a stream of requests of a given type and associated priority. Under normal circumstances in which resource buffer availability for a destination device is not an issue, higher priority streams are provided grants over lower priority streams, with all streams receiving grants. However, when a resource buffer is not available for a lower priority stream, arbitration of high priority streams with available buffer resources are redirected to the low priority arbitration pool, resulting in generation of grant counts for both the higher and lower priority streams. When the resource buffer for the low priority stream becomes available and a corresponding request is arbitrated in the high priority arbitration pool, a grant for the request can be immediately made since grant counts for the stream already exist.

Starvation prevention scheme for a fixed priority PCE-express arbiter with grant counters using arbitration pools

Starvation prevention scheme for a fixed priority PCI-Express arbiter with grant counters using arbitration pools

Growing community of inventors

Bayan Lepas, Malaysia

Khee Wooi Lee