Sandisk Technologies Inc.

Cisco Technology, Inc.

Khanh Vinh Nguyen

Kenneth Louie

Naveen Kumar Tyagi

Man Lung Mui

Hao Nguyen

Yingda Dong

Seungpil Lee

Jagdish Sabde

Sagar Magia

Toru Ishigaki

Patrick Daniel Wildi

Aniruddh S Dikhit

Chang Hua Siau

Grishma Shah

Ali K Al-Shamma

Farookh Moogat

Qui V Nguyen

Jong Hak Yuh

James B Hart

Nir Ben-Dvora

Amul Dhirajbhai Desai

Rajan Paudel

Kapil Verma

Ray Mein Lau

Douglas Roger Banks

Harinadh Nagulapalli

Bojesha Nagaraja

Kenneth Se Mon Louie

Thomas W Richter

Abhilash Sreedharan Nair Mannathanil

Techniques for orchestrating a workflow for configuring a computer networking environment or other complex workflows are described. A Directed Acyclic Graph (DAG) that defines a plurality of tasks to be executed to complete the workflow and a plurality of orders between the tasks is received. Embodiments generate a State-Machine Neural Network (SNN) based on the received DAG, by generating a plurality of SNN neurons for the SNN, based on the plurality of tasks within the received DAG and generating a plurality of SNN connections for the SNN, connecting pairs of SNN neurons within the plurality of SNN neurons, based on the plurality of connections within the received DAG. The SNN is executed to orchestrate the workflow by sending and receiving signals to and from the SNN neurons.

Network automation and orchestration using state-machine neural networks

A data management system and associated data management method is disclosed herein. An exemplary method for managing data includes receiving data records timestamped with times spanned by a defined time interval; generating a data cube that includes data planes, wherein each data plane contains a set of data records timestamped with times spanned by the defined time interval; generating an index hypercube for the data cube, wherein dimensions of the index hypercube represent hash values of index keys defined for accessing the data cube; and generating an indexed data cube for storing in a database, wherein the indexed data cube includes the data cube and the index hypercube. The index hypercube includes index hypercube elements, where each index hypercube element represents a unique combination of hashed index key values that map to a data plane in the data cube.

Fast circular database

Embodiments herein describe a retroactive tracer that retroactively generates traces using data stored in local caches. Rather than continually generating and collecting tracing data in a distributed system (which may requires massive amounts of storage and bandwidth), the embodiments herein store tracing data in local caches corresponding to nodes in the distributed system (e.g., a service, application, virtual machine, server, network device, etc.). When an error is detected when executing a task, the retroactive tracer can broadcast a request that the nodes send any trace data they may have corresponding to that task. The tracer can then retroactively generate the trace from the collected trace data. In contrast, if a task completes without an error, the nodes delete the trace data from their local caches (i.e., the trace data is not collected by the retroactive tracer).

Retroactive tracing in a distributed system

In one embodiment, a method comprises generating, by a computing device from first and second images of a projected pattern of laser dots detected by respective camera devices in a physical environment, a stereoscopic two-dimensional (2D) object pair based on determining 2D positions for each of the laser dots detected in the first and second images, creating a first mesh of geometric patterns from the 2D positions in the first image and a corresponding second mesh of the geometric patterns from the 2D positions in the second image, and creating the stereoscopic 2D object pair based on matching corresponding geometric patterns from the first and second meshes of the geometric patterns. A three-dimensional model (3D) of the physical environment is generated based on executing stereoscopic triangulation of the stereoscopic 2D object pair. The 3D model causes a controllable device to interact with the physical environment.

Three-dimensional computer vision based on projected pattern of laser dots and geometric pattern matching

Disclosed includes a memory device and a method of operating the memory device. A voltage is applied to a word line coupled to first memory transistors of a first plurality of strings of transistors and second memory transistors of a second plurality of strings of transistors. A current flow through one or more of the first plurality of strings of transistors is enabled, while applying the voltage to the word line. A current flow through the second plurality of strings of transistors is disabled by floating source terminals and drain terminals of the second memory transistors, while enabling the current flow through the one or more of the first plurality of strings of transistors.

Select gates separation for improving performance in three-dimensional non-volatile memory

Apparatuses, systems, methods, and computer program products are disclosed for dynamic strobe timing. A controller is configured to generate a strobe signal to facilitate data transfer. A controller is configured to receive a feedback signal in response to initiation of a strobe signal. A controller is configured to control a duration of a strobe signal based on a feedback signal.

Dynamic strobe timing

In a non-volatile memory formed according to a NAND-type architecture that has, on one or both ends of the NAND strings, multiple select gates including some with programmable threshold voltages, a structure and corresponding for efficiently programming of such select gates. On the drain side, the end most of multiple drain select transistors is individually controllable and used for biasing purposes while one or more other drain side select gates are collectively programmed to set adjust their threshold voltage. Independently, on the source side, the end most of multiple source select transistors is individually controllable and used for biasing purposes while other source side select gates are collectively programmed to set adjust their threshold voltage.

Techniques for programming of select gates in NAND memory

A number of techniques for determining defects in non-volatile memory arrays are presented, which are particularly applicable to 3D NAND memory, such as that of the BiCS type. Word line to word shorts within a memory block are determined by application of an AC stress mode, followed by a defect detection operation. An inter-block stress and detection operation can be used determine word line to word line leaks between different blocks. Select gate leak line leakage, both the word lines and other select lines, is consider, as are shorts from word lines and select lines to local source lines. In addition to word line and select line defects, techniques for determining shorts between bit lines and low voltage circuitry, as in the sense amplifiers, are presented.

Determination of word line to word line shorts between adjacent blocks

A method is provided in one example and includes receiving flow data associated with a traffic flow. The flow data can be tagged with a data source identifier identifying a data source exporting the flow data, a source site identifier identifying a site associated with a source device of the traffic flow, and a destination site identifier identifying a destination site associated with a destination device of the traffic flow. The method further includes determining at least one authoritative data source for each site and metric type using at least one selection rule. The method further includes receiving a query for de-duplicated flow data, and generating de-duplicated flow data based on the data source identifier, source site identifier, and destination site identifier and particular flow data associated with the determined at least one authoritative data source.

Flow de-duplication for network monitoring

Systems and methods for reducing peak power supply current in a non-volatile memory system that includes a plurality of memory die are described. In some cases, prior to a first memory die of the plurality of memory die performing a particular memory operation (e.g., a programming operation), the first memory die may poll other memory die of the plurality of memory die to determine a total peak power supply current for the plurality of memory die. In response to detecting that the total peak power supply current for the plurality of memory die is at or above a peak current threshold (e.g., more than 200 mA), the first memory die may delay the performance of the particular memory operation or slow down the performance of the particular memory operation.

Ad hoc digital multi-die polling for peak ICC management

When performing an erase on a flash type non-volatile memory with a NAND type of structure, techniques are presented for inhibiting erase on selected word lines, select lines of programmable select transistors, or some combination of these. The voltage along the selected control lines are initially ramped up by the level on a corresponding input line, but then have their voltage raised to an erase inhibit level by capacitive coupling with the well structure. The level of these input signals are ramped up with the erase voltage applied to the well structure, but with a delay based upon the coupling ratio between the control line and the well.

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Milpitas, CA, United States of America

Khanh Vinh Nguyen