International Business Machines Corporation

Dell Products Inc.

Repsol, S.a.

Khanh Tuan Nguyen

Young-Hye Na

Tai Anh Cao

Robert Dennis Miller

Hieu T Ngo

Sogol Teschler

Younes Ansari

Aquilur Rahman

Francisco José Alía Moreno-Ortiz

Disclosed is a rapid, reproducible solution-based method to synthesize solid sodium ion-conductive materials. The method includes: (a) forming an aqueous mixture of (i) at least one sodium salt, and (ii) at least one metal oxide; (b) adding at least one phosphorous precursor as a neutralizing agent into the mixture; (c) concentrating the mixture to form a paste; (d) calcining or removing liquid from the paste to form a solid; and (e) sintering the solid at a high temperature to form a dense, non-porous, sodium ion-conductive material. Solid sodium ion-conductive materials have electrochemical applications, including use as solid electrolytes for batteries.

Facile synthesis of solid sodium ion-conductive electrolytes

A method includes applying to a substrate a solution including a polymeric compound to form a release layer on the substrate; applying ion-conducting elements on the release layer; applying a matrix polymer on the release layer, wherein the matrix polymer surrounds at least some of the ion-conducting elements; and removing the release layer to separate the matrix polymer from the substrate such that the ion-conducting elements remain embedded in a carrier layer of the matrix polymer and form an ion-conducting membrane.

Release layer for preparation of ion-conducting membranes

Release layer for preparation of ion conducting membranes

For testing a device under test ('DUT') a test specification is converted in a computer system by a pin vector generator process, which includes generating test vectors. The DUT has numerous input pins and such a pin vector is for a signal to drive one such pin. The pin vectors are compressed and saved. Ones of the pin vectors are loaded, upon initialization of a test, into a pipeline having a series of memory stages and extending from the computer system to channel cards in a test head. The pipeline is operated in data transfer cycles, delivering W bits per cycle. The pin vectors are decompressed at the respective channel cards in decompressor read cycles. X bits are read per decompressor cycle, W being greater than X, so that the pipeline may perform its data transfer cycles less frequently than the decompressor performs its read cycles.

Method, apparatus and computer program product for high speed memory testing

A system for providing an error indication of video data received from a first link of a data interface between a computer system video controller and a display system and for providing the error indication to the video controller from the display system via a second link of the data interface. Such a system can be utilized to determine if an error condition exits in the video data path between the video controller and display system. In one example, the data interface conforms to the Digital Visual Interface (DVI) specification. A diagnostic routine of an operating system can be utilized to generate a set of test video data and compare the generated error indication with a standard error indication to determined an error condition. Also, such a system allows a remote system to request a test of the video data path. In one embodiment, the error indication is provided to the video controller from the display system by inserting the error indication into a display information data structure such as, e.g., an Extended Display Identification Data (EDID) structure.

Video data error detection

An exclusive OR circuit (10) includes an input stage (11) and a control arrangement (12,13) for controlling an exclusive OR logical evaluation. The control arrangement includes a pre-charge stage (12) which responds to a first level clock signal to enable the desired exclusive OR logical evaluation. The input stage (11) is connected to receive a first input signal and a second input signal and is also connected to an evaluation node (23). When the logic state of one input signal is unequal to the logic state of the other input signal, the input stage (11) couples the evaluation node (23) to ground. An output stage (13) of the control arrangement inverts the signal at an internal node (24) to produce the output from the exclusive OR circuit. A pre-charge stage (12) couples the internal node (24) to the evaluation node (23) only in response to a 'high' clock signal. Coupling the internal node (24) and evaluation node (23) allows the internal node to follow the state of the evaluation node and produce the desired exclusive OR evaluation through the output stage (13).

Clock controlled exclusive or circuit

A voltage converter circuit (10) includes a primary P-type FET (20) having its source-drain conduction path connected between an input (22) and a first output node (23). An N-type FET (21) is connected in parallel with the primary P-type device (20) between the input (22) and first output node (23). The gate electrode of the primary P-type device (20) is connected to the first output node (23) while the gate electrode of the N-type device (21) is connected to a second voltage supply at the voltage level of a desired second voltage signal. A first digital signal at a first voltage level is applied to the input (22). The voltage produced at the first output node (23) equals the desired second voltage level and comprises the input signal voltage reduced by the threshold voltage of the primary P-type device (20). One or more additional P-type devices (40) may be connected in series with the primary P-type device (20) to reduce the output voltage level further.

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Austin, TX, United States of America

Khanh Tuan Nguyen