Advanced Micro Devices Corporation

Real Action Paintball Inc.

Real Action Paintball (rap4), Inc.

Semix Incorporated

Khanh Q Tran

Jeffrey Allan Shields

Robert C Chen

Robert Louis Dawson

Paul Raymond Besser

Sunil D Mehta

Richard J Huang

Minh Van Ngo

Lu You

Andre N Stolmeijer

Matthew S Buynoski

Simon S Chan

Jean Y Yang

Guarionex Morales

Omar Alonso Macy

Loc T Pham

John Caffall

Nick Maccrae

Shekhar Pramanick

Raymond T Lee

Scott Luning

David W Wu

Terri Jo Kitson

Jeff Shields

Guy Mendez

Arin Chang

Tom Kelly

The present disclosure provides a foldable buttstock assembly for a pneumatic air gun. The foldable buttstock assembly has a foldable buttstock air fitting adapter connected to an air tank to a barrel unit of the pneumatic air gun. It also has an air channeling fitting to channel flow of the air gas. The pneumatic air gun can be operated while the air tank is in any position.

Foldable buttstock having air tank in different positions for pneumatic air gun

A paintball assembly capable of retaining a paintball in a loading chamber using a paintball catcher is disclosed. The paintball assembly includes a loading chamber, a detent, and a bolt. The loading chamber is coupled to a loading port to receive paintballs. In one embodiment, the detent includes a paintball catcher capable of catching the paintball as it is loaded into the loading chamber. In one example, the paintball catcher is a flexible paintball catcher extending into the loading chamber and is able to catch the paintball and hold it in a predefined position. When a trigger is pulled, the bolt pushes the paintball into a firing chamber while the paintball catcher releases the paintball.

Method and apparatus for controlling paintball loading using a detent

A bottom feed magazine of a paintball gun includes a housing for storing a plurality of paintballs. A circular tray is mounted to the housing. A hub is rotatable about a shaft within the circular tray at a center thereof. The circular tray and the hub together define an annular channel for receiving paintballs dropped therein from the housing. A plurality of arms is provided on the hub for driving the paintballs along the channel. A tube has an inlet end extending into the channel and an outlet end extending generally upwards to a top wall of the housing. When the central hub rotates, the paintballs in the channel are driven along the channel, into the inlet end and pushed up along the tube towards the outlet end.

Bottom feed magazine of paintball gun

A simulated land mine for use in a combat simulation or a simulated war game, comprising: a base frame with an opening facing upwards; an inner housing inserted into the base frame and including a first center hole formed vertically therethrough; a gas cylinder mounted in the first center hole and including a second center hole formed vertically therethrough, a gas chamber formed around the second center hole and a discharge aperture communicating the formers and being used for containing compressed gas; a valve mounted in the second center hole for sealing the discharge aperture; a receiving chamber formed at an upper part of the first center hole by the inner housing, the gas cylinder and the valve and being used to contain colored liquid or powder to be ejected; means for supporting the inner housing which enables the movement of the inner housing in relation to the base frame; and a means for actuating the valve to selectively open the discharge aperture to release the compressed gas from the gas chamber into the receiving chamber.

Simulated land mine

A paintball marker includes a main body and a dual feed adapter coupled to the main body. The dual feed adapter has a hollow interior, a top feed port and a bottom feed port. A top feed storage hopper is detachably connected to the dual feed adapter at the top feed port, and a bottom feed storage magazine is detachably connected to the dual feed adapter at the bottom feed port. A sleeve with an opening is rotatable within the dual feed adapter between a first position where the sleeve opening aligns with the top feed port for feeding therethrough a first group of paintballs from the hopper, and a second position where the sleeve opening aligns with the bottom feed port for feeding therethrough a second group of paintballs from the magazine.

Dual feed adapter of paintball marker

Punch-through vias are filled by initially depositing a thin, conformal layer of titanium nitride by chemical vapor deposition to cover an exposed upper surface of a lower metal feature, e.g. portions exposed by penetrating and undercutting an anti-reflective coating. A metal such as tungsten is subsequently deposited to fill the punch-through via. Embodiments include thermal decomposition of an organic-titanium compound, such as tetrakis-dimethylamino titanium, and treating the deposited titanium nitride in an H /N plasma to lower its resistivity. Moreover, the thickness of the anti-reflective coating can be reduced and the process window for etching the via widened.

Punch-through via with conformal barrier liner

A method for making 0.25-micron semiconductor chips includes annealing the metal interconnect lines prior to depositing an inter-layer dielectric (ILD) between the lines. During annealing, an alloy of aluminum and titanium forms, which subsequently volumetrically contracts, with the contraction being absorbed by the aluminum. Because the alloy is reacted prior to ILD deposition, however, the aluminum is not constrained by the ILD when it attempts to absorb the contraction of the alloy. Consequently, the likelihood of undesirable void formation. in the interconnect lines is reduced. The likelihood of undesirable void formation is still further reduced during the subsequent ILD gapfill deposition process by using relatively low bias power to reduce vapor deposition temperature. and by using relatively low source gas deposition flow rates to reduce flow-induced compressive stress on the interconnect lines during ILD formation.

METHOD FOR REDUCING STRESS-INDUCED VOIDS FOR 0.25-&mgr;M AND SMALLER SEMICONDUCTOR CHIP TECHNOLOGY BY ANNEALING INTERCONNECT LINES AND USING LOW BIAS VOLTAGE AND LOW INTERLAYER DIELECTRIC DEPOSITION RATE AND SEMICONDUCTOR CHIP MADE THEREBY

A dielectric interlayer is formed over a semiconductor substrate comprising at least one active region. The exposed upper surface of the dielectric interlayer is treated with nitrogen to form a nitrided barrier layer thereon. At least one hydrogen-containing dielectric layer is formed over the dielectric interlayer having the nitrided barrier layer thereon. The nitrided barrier layer serves as a barrier to diffusion of hydrogen from the at least one hydrogen-containing dielectric layer into the dielectric interlayer, thereby preventing a decrease in hot carrier injection reliability.

H2  diffusion barrier formation by nitrogen incorporation in oxide layer

A method and apparatus are described for transferring processing structures between first and second processing environments. The apparatus includes a first apparatus compartment configured to provide the first processing environment and a second apparatus compartment configured to provide the second processing environment. The apparatus is preferably configured for transferring wafer structures between the processing environments. The first and second processing environments are coupled together through a transfer passage that is opened and closed in order to isolate the wafer in a small transfer volume between the processing environments. Preferably, the transfer passage is opened and closed with first and second movable tables to create the small volume transfer cavity. In operation, the wafer is isolated within the small volume transfer cavity and the first and second tables are individually raised and lowered to expose the wafer to the first and second processing environments without opening the transfer passage between the first and second apparatus compartments. According to an embodiment of the invention, the apparatus is configured with a chemical delivery system that monitors the chemical composition or chemical concentration within the second apparatus compartment and supplies the appropriate quantity of chemical or chemicals to maintain a selected composition or concentration therein. According to a preferred embodiment the apparatus is configured for processing wafers coated with silicon-based materials to produce porous low-k coatings.

Wafer processing apparatus and method

The capacitance between the gate electrode and the source/drain regions of a semiconductor device is reduced by forming sub-spacers of a low dielectric constant (K) material at the corners of the gate electrode above the source/drain regions. Subsequently, insulating sidewall spacers are formed over the sub-spacers to shield-shallow source/drain regions from subsequent impurity implantations. The resulting semiconductor device exhibits reduced capacitance between the gate electrode and the source/drain regions, while maintaining circuit reliability.

Low-K sub spacer pocket formation for gate capacitance reduction

A method for making 0.25 micron semiconductor chips includes annealing the metal interconnect lines prior to depositing an inter-layer dielectric (ILD) between the lines. During annealing, an alloy of aluminum and titanium forms, which subsequently volumetrically contracts, with the contraction being absorbed by the aluminum. Because the alloy is reacted prior to ILD deposition, however, the aluminum is not constrained by the ILD when it attempts to absorb the contraction of the alloy. Consequently, the likelihood of undesirable void formation in the interconnect lines is reduced. The likelihood of undesirable void formation is still further reduced during the subsequent ILD gapfill deposition process by using relatively low bias power to reduce vapor deposition temperature, and by using relatively low source gas deposition flow rates to reduce flow-induced compressive stress on the interconnect lines during ILD formation.

Method for reducing stress-induced voids for 0.25m&mgr; and smaller semiconductor chip technology by annealing interconnect lines and using low bias voltage and low interlayer dielectric deposition rate and semiconductor chip made thereby

Spacings between metal features are gap filled with HSQ. Portions of the deposited HSQ adjoining the side surfaces and upper surface of a metal feature are selectively heated to increase the density and etch resistance of the adjoining HSQ portions, thereby enabling formation of reliable, voidless, low resistance, borderless vias. In an embodiment of the present invention, selective heating is effected by heating a metal line to indirectly heat the adjoining portions of the HSQ layer, as by infrared heating.

Borderless vias with HSQ gap filled metal patterns having high etching resistance

Borderless vias are formed by depositing a hard dielectric mask layer on the upper surface of a lower metal feature and forming sidewall spacers on the side surfaces of the metal feature and mask layer. A dielectric interlayer is deposited and a misaligned through-hole formed therein by etching. The dielectric material of the sidewall spacer and dielectric material of the dielectric interlayer are different. The etchant employed to form the through-hole exhibits a high selectivity with respect to the sidewall spacer material. The dielectric mask layer enables the formation of a sidewall spacer extending above the metal feature such that, after etching to form the misaligned through-hole, the sidewall spacer covers the side surface of the metal feature.

Borderless vias

High integrity borderless vias are formed with a protective sidewall spacer on the exposed side surface of the underlying metal feature before depositing a barrier layer. Embodiments include depositing a dielectric capping layer on a metal feature having an ARC, e.g., TiN, etching to form a through-hole stopping on the capping layer, and then etching the exposed capping layer to form the protective sidewall spacer. Other embodiments include depositing a hard inorganic mask layer on the upper surface of the metal feature before depositing the capping layer, forming the through-hole, and sequentially etching the exposed capping layer to form the protective sidewall spacer and then the inorganic hard mask layer. Further embodiments include metal features without an ARC and retaining the inorganic mask layer on the upper surface of the metal feature.

Growing community of inventors

San Jose, CA, United States of America

Khanh Q Tran