Advanced Micro Devices Corporation

Euv Llc.

Khanh B Nguyen

Harry Jay Levinson

Christopher F Lyons

Fei Wang

Scott Allan Bell

Chih Yuh Yang

Stuart E Brown

Paul W Ackmann

Minh Van Ngo

Marina V Plat

Richard David Edwards

Anna Maria Minvielle

Terri Jo Kitson

Khoi A Phan

Christopher A Spence

Leonard Elliott Klebanoff

Craig S Sander

Christopher Lee Pike

Daniel John Rader

Scott Daniel Hector

Regina Tien Schmidt

Richard H Stulen

Jeff Schefske

In one embodiment, the present invention relates to a method of forming a shallow trench, involving the steps of providing a semiconductor substrate comprising a barrier oxide layer over at the semiconductor substrate and a nitride layer over the barrier oxide layer; depositing an ultra-thin photoresist over the nitride layer, the ultra-thin photoresist having a thickness of about 2,000 &angst; or less; patterning the ultra-thin photoresist to expose a portion of the nitride layer and to define a pattern for the shallow trench; etching the exposed portion of the nitride layer with an etchant having a nitride:photoresist selectivity of at least about 10:1 to expose a portion of the barrier oxide layer; etching the exposed portion of the barrier oxide layer to expose a portion of the semiconductor substrate; and etching the exposed portion of the semiconductor substrate to provide the shallow trench. In another embodiment, the method further involves depositing an insulating filler material into the shallow trench to provide a shallow trench isolation region.

Ultra-thin resist shallow trench process using high selectivity nitride etch

A method of forming a conductor pattern on a base with uneven topography includes placing conductor material on the base, placing a hard mask material on the conductor material, planarizing an exposed surface of the hard mask material, and placing a layer of resist on the hard mask material. The resist is patterned and the patterned resist is used in selectively etching the hard mask material, with the hard mask material used in selectively etching the underlying conductor material. By planarizing the hard mask material prior to placing a layer of resist thereupon, uniformity of the resist coating is enhanced and depth of focus problems in exposing the resist are reduced.

Polished hard mask process for conductor layer patterning

A removable pellicle for a lithographic mask that provides active and robust particle protection, and which utilizes a traditional pellicle and two deployments of thermophoretic protection to keep particles off the mask. The removable pellicle is removably attached via a retaining structure to the mask substrate by magnetic attraction with either contacting or non-contacting magnetic capture mechanisms. The pellicle retaining structural is composed of an anchor piece secured to the mask substrate and a frame member containing a pellicle. The anchor piece and the frame member are in removable contact or non-contact by the magnetic capture or latching mechanism. In one embodiment, the frame member is retained in a floating (non-contact) relation to the anchor piece by magnetic levitation. The frame member and the anchor piece are provided with thermophoretic fins which are interdigitated to prevent particles from reaching the patterned area of the mask. Also, the anchor piece and mask are maintained at a higher temperature than the frame member and pellicle which also prevents particles from reaching the patterned mask area by thermophoresis. The pellicle can be positioned over the mask to provide particle protection during mask handling, inspection, and pumpdown, but which can be removed manually or robotically for lithographic use of the mask.

Removable pellicle for lithographic mask protection and handling

A method of forming a via structure is provided. In the method, a dielectric layer is formed on an anti-reflective coating (ARC) layer covering a first metal layer; and a transition metal layer is formed on the dielectric layer. An ultra-thin photoresist layer is formed on the transition metal layer, and the ultra-thin photoresist layer is patterned with short wavelength radiation to define a pattern for a via. The patterned ultra-thin photoresist layer is used as a mask during a first etch step to transfer the via pattern to the transition metal layer. The first etch step includes an etch chemistry that is selective to the transition metal layer over the ultra-thin photoresist layer and the dielectric layer. The transition metal layer is employed as a hard mask during a second etch step to form a contact hole corresponding to the via pattern by etching portions of the dielectric layer.

Thin resist with transition metal hard mask for via etch application

A method of identifying a change in focus and a change in illumination from a best focus and a best dose at a region on a substrate corresponding to a point in the image field of a lithographic printing tool is disclosed. The method includes forming a feature having a first pitch and a feature having a second pitch at the region on the substrate, and identifying a linewidth of the features. The identified linewidths are then used to determine the change in focus from the best focus and the change in dose from the best dose which would produce both the first pitch feature and the second pitch feature at the region.

Technique to separate dose-induced vs. focus-induced CD or linewidth variation

A structure ( ) for determining an amount of line edge roughness (LER) on a patterned feature ( ) includes a plurality of source regions ( ) and drain regions ( ) formed in a semiconductor substrate ( ), with each of the source and drain regions ( ) having a channel ( ) therebetween. The source regions ( ) are electrically isolated from each other and the drain regions ( ) are electrically isolated from each other, respectively. The patterned feature of interest ( ) is formed over a gate oxide, extends over the channels ( ) in a direction which is transverse to the source regions ( ) and the drain regions ( ), and forms a common gate ( ) for a plurality of transistors ( ) formed with the plurality of source regions ( ) and drain regions ( ). The plurality of transistors ( ) are activated to conduct current therethrough by placing a predetermined voltage on the common gate ( ) and the currents of the plurality of transistors ( ) are used to determine the line edge roughness (LER) of the patterned feature

Device to determine line edge roughness effect on device performance

There is provided a method for applying a lower viscosity coating liquid onto a semiconductor wafer substrate so as to prevent adhesion loss and to maintain low defect level characteristics. This is achieved by priming the substrate with a bonding agent at a temperature in the range of 18&deg; C. to 50&deg; C. for a short amount of time. This is performed prior to the application of a liquid solvent. As a result, there is overcome the problems of poor adhesion to the substrates and high defect levels in the coated UTR films.

Method for coating ultra-thin resist films

There is provided a method for enhancing the contrast between oxide film and ultra-thin resists in deep-ultraviolet lithography for use with a wafer defect inspection system in order to maximize defect inspection sensitivity. This is achieved by varying the thickness of the oxide film for a given ultra-thin resist thickness so as to produce a high contrast. As a result, defect inspection of the ultra-thin resist pattern is easily obtained. In a second embodiment, the ultra-thin resist thickness is varied for a given oxide film thickness. In a third embodiment, both the oxide film and the ultra-thin resist thicknesses are varied simultaneously so as to obtain an optimum contrast.

Tuning substrate/resist contrast to maximize defect inspection sensitivity for ultra-thin resist in DUV lithography

A method of forming a gate structure is provided. In the method, a nitride layer is formed on a gate material layer. An ultra-thin photoresist layer is formed on the nitride layer. The ultra-thin photoresist layer is patterned with short wavelength radiation to define a pattern for the gate. The ultra-thin photoresist layer is used as a mask during a first etch step to transfer the gate pattern to the nitride layer. The first etch step includes an etch chemistry that is selective to the nitride layer over the ultra-thin photoresist layer. The nitride layer is used as a hard mask during a second etch step to form the gate by transferring the gate pattern to the gate material layer via the second etch step.

Thin resist with nitride hard mask for gate etch application

In one embodiment, the present invention relates to a method of forming a metal line, involving the steps of providing a semiconductor substrate comprising a metal layer, an oxide layer over the metal layer, and a silicon oxynitride layer over the oxide layer; depositing an ultra-thin photoresist over the silicon oxynitride layer, the ultra-thin photoresist having a thickness less than about 2,000 &angst;; irradiating the ultra-thin photoresist with electromagnetic radiation having a wavelength of about 250 nm or less; developing the ultra-thin photoresist exposing a portion of the silicon oxynitride layer; etching the exposed portion of the silicon oxynitride layer exposing a portion of the oxide layer; etching the exposed portion of the oxide layer exposing a portion of the metal layer; and etching the exposed portion of the metal layer thereby forming the metal line.

Ultra-thin resist and SiON/oxide hard mask for metal etch

A method for processing a semiconductor substrate is presented wherein an alignment mark is formed in an alignment mark area of the semiconductor substrate. The alignment mark area is contained within a window area of the semiconductor substrate. The upper surface of the semiconductor substrate within the window area is recessed below the upper surface of the semiconductor substrate outside of the window area, preferably by exposing the upper surface of the semiconductor substrate within the window area to an etchant. Such recession forms an alignment mark trench within the window area. Being substantially recessed below the original surface of the semiconductor substrate, an alignment mark formed in such a manner may be substantially protected from chemical-mechanical polishing damage during subsequent processing steps.

Method for reducing the susceptibility to chemical-mechanical polishing damage of an alignment mark formed in a semiconductor substrate

Prior to entering into manufacturing of a final production wafer, a series of test wafers are produced to analyze and test various structures. Each of the test wafers include a substrate, an insulating layer overlying the substrate, and a semi-conductive film layer formed over the insulating layer. The film layer is comprised of, for example, poly-silicon and has a predetermined thickness which substantially corresponds to the thickness of a film layer deposited on the final production wafer. The film layer is etched to form a desired pattern of structures and implanted with a dopant to diffuse dopant atoms thoughout. Thereafter, critical dimension measurements of the structures are taken preferably using electrical line width measurements techniques. Variations in critical dimension measurements taken from the test wafer as compared to desired predetermined line width measurements are compensated for prior to manufacturing the final production wafer so as to provide circuits with the desired electrical parameters.

Method and apparatus for compensating for critical dimension variations in the production of a semiconductor wafer

A method (,) of characterizing a lithographic scanning system includes the steps of printing a first pattern (,) using a reticle (,) having a first orientation with respect to the lithographic scanning system and measuring a critical dimension of the first pattern at a plurality of points (,). The method (,) further includes printing a second pattern (,) using the reticle (,) having a second orientation with respect to the lithographic scanning system different than the first orientation and measuring a critical dimension of the second pattern at the plurality of points (,). The measured critical dimension data is then used to determine a reticle critical dimension component and a non-reticle critical dimension component of the patterns at the plurality of points (,) and a scanning system critical dimension component of the patterns is then determined using the non-reticle critical dimension component data along a plurality of points corresponding to a scanning direction of the lithographic scanning system (,).

Determination of scanning error in scanner by reticle rotation

An alignment mark protection structure (,) is disclosed which is used to ensure an integrity of an alignment scheme for a substrate (,) which is to be subjected to lithographic processing. The alignment mark protection structure (,) comprises the substrate (,) and an alignment mark (,) associated with the substrate (,). The alignment mark (,) reflects an alignment light (,) which is then used to determine an optimum alignment between the substrate (,) and a lithographic mask (,). A cap (,) overlies the alignment mark (,) and is substantially transparent with respect to the alignment light (,). The cap (,) protects the underlying alignment mark (,) from lithographic process-induced damage during processing and thus reduces alignment light noise, thereby improving the alignment between a mask (,) and the substrate (,) and minimizing the registration error associated with overlying layers formed on the substrate (,).

Mark protection with transparent film

In one embodiment, the present invention relates to a method of forming a metal line, involving the steps of providing a semiconductor substrate comprising a metal layer, an oxide layer over the metal layer, and a barrier metal layer over the oxide layer; depositing an ultra-thin photoresist over the barrier metal layer, the ultra-thin photoresist having a thickness less than about 2,000 &angst;; irradiating the ultra-thin photoresist with electromagnetic radiation having a wavelength of about 250 nm or less; developing the ultra-thin photoresist exposing a portion of the barrier metal layer; etching the exposed portion of the barrier metal layer exposing a portion of the oxide layer; etching the exposed portion of the oxide layer exposing a portion of the metal layer; and etching the exposed portion of the metal layer thereby forming the metal line.

Growing community of inventors

San Mateo, CA, United States of America

Khanh B Nguyen