Cadence Design Systems, Inc.

Khalid ElGalaind

Arnold Ginetti

Regis R Colwell

Jeffrey Markham

Chung-Do Yang

Jose A Martinez

Steven Riley

Thomas Jordan

A method is provided to produce a constraint information for use to implement a routing process used to generate routing signal lines in an integrated circuit design comprising: producing a net topology pattern structure that corresponds to a logical net that is associated with at least two instance item structures of at least one functional design, wherein the net topology pattern structure is associated with the at least two instance item structures and includes multiple constituent structures that indicate at least one constraint upon physical implementation of the logical net structure.

Producing a net topology pattern as a constraint upon routing of signal paths in an integrated circuit design

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Allison Park, PA, United States of America

Khalid ElGalaind