Texas Instruments Corporation

Khaled M Sharaf

Abdellatif Bellaouar

Ahmed Reda Fridi

The present invention discusses fractional compensation timing circuitry (,) to track a VCO output frequency, f,, and provide highly effective error cancellation in a fractional-N PLL synthesizer. This output frequency tracking is used to suppress spurious sidebands, commonly known as spurs, in both fixed-band and multi-band wireless transceiver applications which use fractional-N PLL synthesizers. Some of the critical parameters which benefit from this type of PLL include switching time, phase noise, and reference feed-through.

Fractional-spurs suppression scheme in frequency tracking multi-band fractional-N phase lock loop

Multi-band fractional-N PLL synthesizers with built-in spurious sideband compensation, which tracks the VCO output, tend to consume large amounts of power (as much as 10 times) due to the RF operation of the compensation circuitry. This patent introduces a dynamic power approach where the compensation circuitry is biased only during the fractional portion of the cycle. This technique provides the advantages of fractional-N synthesizers with spur suppression, such as higher speed and lower phase noise with ultra low power dissipation.

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Richardson, TX, United States of America

Khaled M Sharaf