Actel Corporation, Inc.

Other

Khaled A El-Ayat

William C Plants

Jia-Hwang Chang

Theodore M Speers

John L McCollum

Abbas A El Gamal

Amr M Mohsen

Limin Zhu

Rabindranath Balasubramanian

Venkatesh Narayanan

Greg Bakker

Brian Schubert

Thomas Barraza

King W Chan

Kurt Kolkind

Gregory William Bakker

Jonathan W Greene

Justin M Reyneri

Ta-Pen R Guo

Sinan Kaptanoglu

Jung-Cheun Lien

Kenneth D Hayes

Kurt Kilkind

Kuthanur R Dharmarajan

Abbas E Gamal

Abbas Elgamal

A programmable system-on-a-chip integrated circuit device comprises a programmable logic block, a non-volatile memory block, an analog sub-system, an analog input/output circuit block, and a digital input/output circuit block. A programmable interconnect architecture includes programmable elements and interconnect conductors. Ones of the programmable elements are coupled to the programmable logic block, the non-volatile memory block, the analog sub-system, the analog input/output circuit block, the digital input/output circuit block, and to the interconnect conductors, such that inputs and outputs of the programmable logic block, the non-volatile memory block, the analog sub-system, the analog input/output circuit block, and the digital input/output circuit block can be programmably coupled to one another.

Programmable system on a chip

The invention discloses an architecture for the input/output buffer section of an FPGA. It provides a convenient and efficient addressing scheme for addressing fuse matrices that are used to configure programmable input/output buffers in the FPGA. The programmable I/O buffers may be configured to implement a large number of different output and input bus standards.

Programmable multi-standard I/O architecture for FPGAS

The invention disclosed an architecture for the input/output buffer section of an FPGA. It provides a convenient and efficient addressing scheme for addressing fuse matrices that are used to configure programmable input/output buffers in the FPGA. The programmable I/O buffers may be configured to implement a large number of different output and input bus standards

Programmable multi-standard I/O architecture for FPGAs

The invention discloses an architecture for the input/output buffer section of an FPGA. It provides a convenient and efficient addressing scheme for addressing fuse matrices that are used to configure programmable input/output buffers in the FPGA. The programmable I/O buffers may be configured to implement a large number of different output and input bus standards

An input/output architecture for a field-programmable gate array integrated circuit including a plurality of logic function modules in an array of rows and columns, each of the modules having at least one input conductor and at least one output conductor; a plurality of interconnect conductors, comprising a plurality of input/output pads; a plurality of input/output kernels, each input/output kernel comprising an input buffer having a data input connected to one of the I/O pads and a data output connected to an input buffer data conductor, an output buffer having a data input connected to an output buffer data conductor, a data output connected to the I/O pad, and an enable input connected to an output buffer enable conductor; the input buffer data conductors extending in either the row or the column direction, different ones of the input buffer data conductors extending different numbers of rows or columns, the input buffer data conductors forming first intersections with inputs of the modules; the output buffer data conductors and output buffer enable conductors extending in either the row or the column direction, different ones of the output buffer data conductors and output buffer enable conductors extending different numbers of rows or columns, the input buffer data conductors forming second intersections with outputs of the modules; and user-programmable interconnect elements connected across selected ones of the first and second intersections.

Flexible FPGA input/output architecture

A user-programmable interconnect architecture, which may be used for logic arrays for digital and analog system design, is disclosed. In one embodiment, a plurality of logic cells or modules in a matrix are connected by vertical and horizontal wiring channels. The wiring channels may in turn be programmed by the user to interconnect the various logic cells to implement the required logic function. The wiring channels comprise wiring segments connected by normally open programmable. Elements situated at the intersection of any two segments to be connected.

Programmable interconnect architecture

User-configurable logic circuits comprising antifuses and

In an integrated circuit having a plurality of function modules, each of the function modules having at least two inputs and at least one output. The integrated circuit is user programmable such that interconnections between selected ones of the function modules and input/output pins on the integrated circuit may be made. The integrated circuit further having two states, a first unprogrammed state where none of the interconnections have been made, and a second, programmed state in which selected interconnections have been made. Circuitry for testing the functionality of individual ones of the function modules when the integrated circuit is in the unprogrammed state comprises addressing means for selecting any one of the function modules, data input means for providing a selected logic level to at least one of the inputs of the function module selected by the addressing means, and output-connecting means, responsive to the addressing means, for temporarily connecting the output of the selected one of the function modules to one of the input/output pins on the integrated circuit.

Testability architecture and techniques for programmable interconnect

A clock distribution architecture is disclosed for use in a user-programmable logic array integrated circuit comprising an array of user-programmable logic elements having inputs and outputs, at least some of the user-programmable logic elements including sequential logic elements having clock inputs, and further including a plurality of general interconnect lines which may be connected to one another and to the inputs and outputs of the logic elements. The clock distribution architecture includes at least one clock input pin on the integrated circuit, a plurality of clock distribution lines disposed in the array, at least one buffer amplifier having an input connected to the clock input pin and an output connected to at least one of the clock distribution lines. At least one inverter has an input connected to at least one of the clock distribution lines, and an output. A multiplexer is associated with each of the sequential logic elements, each of the multiplexers has a first input connected to one of the clock distribution lines, a second input connected to the output of the inverter, and a third input connected to a clock signal line connectable to at least one of the general interconnect line through a user-programmable element, an output connected to the clock input of the sequential element with which it is associated, and control inputs selecting which of the first, second, and third inputs is connected to the output.

Clock distribution scheme for user-programmable logic array architecture

An integrated circuit having a plurality of input/output modules, each of which has input/output modules including an input module section having an input node connected to a unique input/output pin on the integrated circuit and an output node communicating with a unique first internal node in the integrated circuit, and an output module section having an input node communicating with a unique second internal node in the integrated circuit and an output node communicating with the unique input/output pin. Each input/output module is programmable by a user such that its function may be defined as an input module, an output module, or a bi-directional module. The integrated circuit further has two states, a first unprogrammed state where none of the functions of the input/output modules have been defined, and a second, programmed state in which the functions of the input/output modules have been defined by either enabling or disabling the output section of the input/output module. Circuitry for testing the input module section of one of the input/output modules in the unprogrammed state comprises means for temporarily disabling the output section of a unique one of the input/output modules, means for temporarily connecting the output node of the input module section to a test node on said integrated circuit, and means for communicating the state of the test node to a test input/output pin on the integrated circuit.

Growing community of inventors

Cupertino, CA, United States of America

Khaled A El-Ayat