Compaq Computer Corporation, Inc.

Hewlett-Packard Development Company, L.p.

Khaldoun Alzien

Maria L Melo

Phillip A Leech

Parthasarathy Ranganathan

David J Maguire

Charles N Shaver

Todd J Deschepper

Robert C Elliott

Thomas J Flynn

Kenneth B Frame

Christopher Rijken

William R Jacobs

Russell J Wunderlich

Michael Leighton Nash

Phil Leech

An example method comprises establishing, via a first data communication interface of a first computing device, a physical connection to between the first computing device and a second computing device. The method also includes receiving, at the first computing device, input data via a second data communication interface of the first computing device. The method further includes controlling an operation at the first computing device based on the input data when the input data is received prior to establishing the connection. The method further includes routing the input data to the second computing device via an input data switch of the first computing device when the input data is received after establishing the connection.

Input data switches

In one embodiment, a printed circuit board assembly comprises a printed circuit board including a processor, a heat sink mountable to the printed circuit board proximate the processor, and a memory module comprising logic instructions which, when executed by the processor, configure the processor to initiate a processor load routine, collect temperature gradient data during the processor load routine, and verify operation of the heat sink using the temperature gradient data.

Heat sink verification

In a method for managing power consumption among compute nodes having respective power components, an increase in the power utilization of a first compute node of the compute nodes may be detected. In response to a detected increase, a sum of the power consumption levels of the compute nodes and the requested increase in power utilization of the first compute node is compared with an allowable power budget for a compute node pool. In addition, the power state of the first compute node power component is varied in response to the comparison.

Power consumption management among compute nodes

A power management agent for managing power among electronic systems includes a module for predicting a future power consumption level of the electronic systems, a module for determining a power budget threshold for the electronic systems, and a module for determining whether a predicted future power consumption level will exceed the power budget threshold. The power management agent also includes a module for selecting one or more of the electronic systems to throttle in response to a determination that the predicted future power consumption level will exceed the power budget threshold and a module for selecting a throttle level to be applied to the selected one or more of the electronic systems to substantially prevent the future power consumption level from exceeding the power budget threshold.

Agent for managing power among electronic systems

A system for managing heterogeneous supply of power includes a plurality of heterogeneous power supplies having a primary power supply and a secondary power supply. The primary power supply has a first power rating and the secondary power supply has a second power rating, where the first power rating differs from the second power rating. In addition, power is supplied to the electronic system through at least one of the primary power supply and the secondary power supply.

Heterogeneous power supply management system

In a method for estimating a condition of an electronic device, a model correlating at least one utilization metric of a component of the electronic device and the condition of the component to be estimated is formulated. In addition, the at least one utilization metric of the component is detected and the condition of the component and the electronic device are estimated based upon the formulated model with the detected at least one utilization metric as an input to the formulated model.

Estimating an electronic device condition

In one embodiment, a printed circuit board assembly comprises a heat sink having an electrically conductive mounting support and a printed circuit board including detection circuitry to detect an electrical connection between the electrically conductive mounting support and an electrically conductive receiver on the printed circuit board.

Heat sink detection

A computer system includes a bus bridge which provides an interface between a processor bus, a main memory and a peripheral bus such as a PCI or AGP bus. When a cycle to memory is initiated on the PCI or AGP bus by a peripheral device, a snoop control circuit of the bus bridge arbitrates for the processor bus to initiate a snoop cycle which corresponds to the line being accessed by the peripheral device. In addition to performing a snoop for the current line being accessed, the snoop control circuit further advantageously runs a speculative snoop cycle for the next sequential line. By performing a speculative snoop cycle on the CPU bus to the next line address, latencies associated with subsequent accesses to memory by the peripheral device may be reduced if the device performs a subsequent sequential access. Furthermore, since the bus bridge performs multiple snoop cycles per arbitration cycle (e.g., multiple snoop cycles are effectuated with only one BPRI_assertion), bandwidth on the CPU bus may be optimized since a CPU bus arbitration cycle may be avoided for the snoop to the sequential line address.

Computer system and method employing speculative snooping for optimizing performance

A bridge logic unit provides an interface between a microprocessor coupled to a processor bus, a main memory coupled to memory bus, and a peripheral device coupled to a peripheral bus, such as a PCI bus. To maintain coherency, the bridge logic unit disables write posting in certain specific situations, and flushes posted write transactions before allowing certain read requests to be serviced. More specifically, in one embodiment when a PCI device performs a read to main memory, which may be implemented within the bridge as delayed read, the bus bridge blocks CPU to PCI transactions and flushes any posted CPU to PCI transactions pending in the bridge. The bus bridge enables CPU to PCI posting after the pending CPU to PCI transactions have been flushed and after the snoop phase of a snoop cycle corresponding to the memory read operation completes. In a further embodiment, prior to performing a PCI read cycle on behalf of a read cycle initiated by the microprocessor, the bus bridge determines whether any PCI to memory transactions are pending in the PCI slave transient write buffer. If any posted write transactions reside in the PCI slave transient write buffer, the bus bridge retries the read cycle on the processor bus and blocks any subsequent posting of write transactions to memory from the PCI bus. When the pending PCI to memory transactions have been flushed from the PCI slave transient write buffer, and the microprocessor reattempts the read, the read cycle is initiated on the PCI bus. At this point, PCI to memory write posting is re-enabled.

System and method for maintaining coherency and improving performance in a bus bridge supporting write posting operations

A computer having a bus interface unit coupled between a CPU bus and a PCI bus and/or a bus interface unit coupled between a PCI bus and memory and or I/O space. The clocking to the configuration space of the bus interface unit can be inhibited to conserve power in two ways. The first approach relies on an input/output address space containing a configuration address register. An enable bit or flag within the configuration address register can be set to allow a determination of the various PCI devices and to configure those devices linked to the PCI bus. Subsequent to computer boot up or initialization, the enable bit can be disabled to disallow further accesses to the configuration address space of the PCI device or PCI compliant bus interface unit. Disabling the enable bit further inhibits or disconnects a clocking signal from sequential logic within the configuration address space to minimize power consumption of the north bridge during its normal operation. In the second approach, the clocking to the configuration space is automatically enabled and disabled as needed by the bus interface unit to transfer data to and from its configuration registers. Removing the clocking signal, in either approach, minimizes power consumption allowing additional functions to be added to the mobile PC.

Configuration logic within a PCI compliant bus interface unit which can be selectively disconnected from a clocking source to conserve power

A computer system includes a bus bridge which provides an interface between a main memory and a peripheral bus such as a PCI bus. A peripheral bus interface unit is provided which supports delayed transactions. When a PCI bus master effectuates a read cycle to read data from main memory on the PCI bus, the peripheral bus interface detects the read cycle and terminates or retries the transaction on the PCI bus. The peripheral bus interface further requests the read data from main memory and places the read data in a buffer. When the PCI master device re-attempts the read transaction, the peripheral interface provides the read data directly from its delayed read buffer. When the peripheral bus interface retries the PCI master that establishes a delayed read operation, the peripheral bus interface asserts a control signal referred to the delayed cycle signal. A PCI arbiter which controls ownership of the PCI bus receives the delayed cycle signal and, in response to its assertion, lowers a level of arbitration priority provided to the PCI master establishing the delayed read. In one embodiment, the PCI arbiter inhibits ownership of the PCI bus by the master establishing the delayed read in response to assertion of the delayed cycle signal. When the peripheral bus interface receives the read data and is ready to deliver it to the PCI bus, the delayed cycle signal is deasserted (or strobed). The PCI bus arbiter detects this deassertion (or strobing) of the delayed cycle signal and responsively raises a level of arbitration priority to the PCI master establishing the delayed read. In one implementation, upon detecting the deassertion of the delayed cycle signal, the PCI bus arbiter provides a highest level of arbitration priority to the PCI master establishing the delayed read. The delayed read operation then completes when the PCI master re-initiates the read cycle. The optimized arbitration technique may similarly be employed during other delayed transactions, such as memory writes, I/O read or writes, and configuration reads or writes.

Computer system employing optimized delayed transaction arbitration technique

A PCI bridge is configured to perform delayed read operations in response to a memory read initiated on the PCI bus. Normally, the PCI bridge is configured to discard delayed read data read from main memory following a predetermined discard count time after the PCI master establishing the delayed read operation is retried on the PCI bus. The computer system further includes a secondary bus bridge such as an ISA bridge for providing an interface between the PCI bus and an ISA bus. When an ISA device desires to read data from the main memory, the ISA bridge asserts a flush request signal. The PCI bridge responsively flushes any pending CPU to PCI transactions pending within the PCI bridge. When the flushing operation is complete, the PCI bridge asserts an acknowledge signal. A PCI arbiter for arbitrating ownership of the PCI bus may increase a level of arbitration priority provided to the ISA bridge in response to assertion of the acknowledge signal. The PCI bridge is advantageously configured to decrease the time associated with discarding of the delayed read data when the acknowledge signal is asserted.

Dynamic delayed transaction discard counter in a bus bridge of a

A PCI repeater coupled between a primary bus and a secondary bus includes logic to allow downstream and upstream bursting across the repeater. The PCI repeater echoes transactions in either an upstream or downstream direction, and does not need any additional address decode logic. The buses are coupled to an arbiter so that only one bus master has control of the bus. During a burst operation, the PCI repeater causes the arbiter to cease providing grant signals to prospective bus grantees. The signal is removed only after the transaction has completed on both sides of the PCI repeater to ensure that the PCI repeater is ready for a next transaction.

PCI to PCI bridge for transparently completing transactions between

A PCI repeater coupled between a primary bus and a secondary bus includes logic to allow downstream and upstream bursting across the repeater. The PCI repeater is operable to echo transactions in either an upstream or downstream direction. During configuration, the PCI repeater snoops configuration cycles on the primary bus to build an address map of devices on the primary bus. The PCI repeater then uses the address map as a lookup table as a positive determination of whether to forward a transaction upstream.

Transparent PCI to PCI bridge with dynamic memory and I/O map programming

A PCI repeater coupled between a primary bus and a secondary bus transparently decodes upstream transactions by halting operations on the secondary bus while the transaction is decoded on the primary bus. A clock disable signal is internally generated to temporarily disable the bus clock on the secondary bus. Transactions initiated on the secondary bus are first sent upstream regardless of whether or not the target is upstream. If the transaction is not positively claimed by a target on the upstream bus, the PCI repeater subtractively claims the transaction. Special upstream decoding logic in the PCI repeater is avoided by sending the transaction upstream and using the inherent decoding logic of PCI devices.

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Houston, TX, United States of America

Khaldoun Alzien