Altera Corporation

Khai Nguyen

Chiakang Sung

Bonnie I Wang

Xiaobao Wang

Joseph Huang

In Whan Kim

Yan Chong

Philip Pan

Tzung-Chin Chang

Wayne Yeung

Gopinath Rangan

Gopi Rangan

Richard G Cliff

John Henry Bui

Phillip Pan

Jeffrey Tyhach

Jonathan Chung

Thomas Henry White

Henry Kim

Warren Nordyke

Sanjay K Charagulla

Ket Chiew Sia

Surgey Y Shumarayev

Myron Wai Wong

Nitin Prasad

Sean Shau-Tu Lu

Wilma Waiman Shiao

Lay Hock Khoo

Bonnie L Wang

Xiabao Wang

Tony K Ngai

Hong Shi

Boon Jin Ang

Dirk Alan Reese

Ali H Burney

Zhe Li

Pradeep Nagarajan

Zahir Parpia

Guy Dupenloup

Ee Mei Ooi

Kin Hong Au

Foong Tek Chan

Wira Gunawan

Im Whan Kim

Khai Huang

Boonie I Wang

A buffer circuit with an adjustable reference voltage is presented. The buffer circuit with adjustable reference voltage has an input buffer circuit that is connected to a data input and a reference voltage. The output of the input buffer circuit is connected an eye monitor circuit that generates a transition signal based on a number of transitions of an output of the input buffer circuit. The output from the eye monitor circuit is that processed by a calibration control circuit that transmits a selection signal to a multiplexer. The multiplexer selects a level of the reference voltage based on the selection signal from the calibration control circuit.

On-die input reference voltage with self-calibrating duty cycle correction

To achieve an even distribution of different types of connections, sets of connection cells have been devised having different ratios of signal, power and ground connections in which the signal connections are all within a maximum distance of a power and/or a ground connection. In addition, the shapes of the cells are such that the cells fit together in a repeatable array that fully covers the plane of the interface, i.e., an array that tiles the plane. Accordingly, to distribute the connections substantially uniformly across the interface, the ratio of the number of signal connections, power connections and ground connections is determined; a cell is selected from the set of cells that has approximately the same ratio of the number of signal connections, power connections and ground connections; and the selected cell is repeatedly used to allocate the signal, power and ground connections in accordance with the distribution of connections in the selected cell until all the connections are distributed.

Distribution of return paths for improved impedance control and reduced crosstalk

Methods and apparatus for providing either high-speed, or lower-speed, flexible inputs and outputs. An input and output structure having a high-speed input, a high-speed output, a low or moderate speed input, and an low or moderate speed output is provided. One of the input and output circuits are selected and the others are deselected. The high-speed input and output circuits are comparatively simple, in one example having only a clear signal for a control line input, and are able to interface to lower speed circuitry inside the core of an integrated circuit. The low or moderate speed input and output circuits are more flexible, for example, having preset, enable, and clear as control line inputs, and are able to support JTAG boundary testing. These parallel high and lower speed circuits are user selectable such that the input output structure is optimized between speed and functionality depending on the requirements of the application.

Programmable high-speed I/O interface

A high speed IO buffer is disclosed. The high speed IO buffer includes a first P-type metal oxide semiconductor (PMOS) transistor coupled to an IO voltage source. The high speed IO buffer also includes a first N-type metal oxide semiconductor (NMOS) transistor coupled to a ground source, a second PMOS transistor coupled to the first PMOS transistor and a pad and a second NMOS transistor coupled to the first NMOS transistor and the pad. The first PMOS transistor, the first NMOS transistor, the second PMOS transistor and the second NMOS transistor are arranged in a cascoded arrangement.

High speed IO buffer

Integrated circuits may include memory interface circuitry that communicates with memory. The memory interface circuitry may include latch circuitry that receives a data strobe enable signal from the memory controller and latches the data strobe enable signal using a data strobe signal received from the memory. The integrated circuit may include logic circuitry that gates the data strobe signal using the latched data strobe enable signal. The logic circuitry may pass the data strobe signal in response to activation of the latched data strobe enable signal. The integrated circuit may include counter circuitry that monitors the gated data strobe signal. The counter circuitry may monitor the gated data strobe signal by counting pulses in the gated data strobe signal to produce a counter value. When the counter value reaches a target value, the logic circuitry may block the data strobe signal from passing to the memory controller.

Memory interface circuitry with improved timing margins

An integrated circuit in a multi-chip package is provided. The integrated circuit may include adjustable interface circuitry configured to interface with other off-chip components. In particular, the adjustable interface circuitry may include a microbump input-output buffer operable to drive signals off of the integrated circuit and operable to receive signals from other integrated circuits in the multi-chip package via a microbump. The microbump input-output buffer may include output buffers and input buffers. The output buffers may have programmable drive strengths and may each be selectively switched in and out of use depending on the desired application. Each output buffer may include a level shifter, a buffer circuit, and multiple inverter-like circuits each of which can be turned on or off to adjust the drive strength of that output buffer.

Adjustable drive strength input-output buffer circuitry

Integrated circuits with clock generation and distribution circuitry are provided. Integrated circuits may include phase-locked loops configured to generate multiple clock signals that are delayed versions of one another. The clocks signal may be distributed to various regions on an integrated circuit using serially connected clock buffer blocks. Each buffer block may include bidirectional pairs of buffer circuits coupled in parallel. Each buffer circuit may have a first input configured to receive an input clock signal, an output at which a corrected version of the input clock signal is provided (e.g., an output at which an output clock signal with desired duty cycle is provided), a second input that receives a first delayed clock signal for setting the desired duty cycle for the output clock signal, and a third input that receives a second delayed clock signal that is high at least when the first delayed clock signal rises high.

Duty cycle distortion correction circuitry

An integrated circuit may include memory interface circuitry that is used to communicate with off-chip memory. The memory interface circuitry may include data strobe (DQS) enable circuitry that receives DQS signals from the off-chip memory and that outputs a gated version of the DQS signals. The DQS enable circuitry may include an input buffer, a comparator, a latch, a flip-flop, a counter, and a gating circuit. The input buffer may receive an incoming DQS signal. The comparator may be used to determine when the incoming DQS signal starts to toggle. The latch may be used to control when a gating signal is asserted. The flip-flop controls the counter, which limits the duration that the gating signal is asserted. The gating circuit receives the DQS signal from the buffer and the gating signal and passes the DQS signal through to its output only when the gating signal is asserted.

Data strobe enable circuitry

Circuits, methods, and apparatus for dynamic control of source and termination impedances. One output stage provides a series termination when transmitting and a parallel termination when receiving data. A pull-up device has a nominal impedance of 50 ohms when the output stage pulls a pin from a low voltage to a high voltage, while a pull-down device has a nominal impedance of 50 ohms when the pin is pulled from a high voltage to a low voltage. Both the pull-up and pull-down devices are turned on when receiving data. Due to their non-linear current-voltage characteristics, the pull-up device appears as 50 ohms when the pin voltage is higher than one half the supply voltage, while the pull-down device appears as 50 ohms when the pin voltage is lower than one half the supply voltage. The pull-up and pull-down devices can be calibrated to provide a nominal 50 ohm impedance.

Dynamic termination-impedance control for bidirectional I/O pins

An integrated circuit includes a clock circuit that may be used to provide clock signals to multiple input-output circuits. The integrated circuit may also include different clock structures. As an example, one of the clock structures may have multiple clock paths of substantially equal lengths while another clock structure may have a fly-by clock path. The multiple clock paths may be used to convey a subset of the clock signals to the input-output circuits. Similarly, the fly-by clock path may be used to transmit a second subset of the clock signals to the input-output circuits.

Clock structure with calibration circuitry

Circuits and techniques for operating an integrated circuit (IC) with a level shifter circuit are disclosed. A level shifter circuit with input and output terminals is operable to shift an input signal that ranges from a ground voltage to a first positive voltage to an output signal that ranges from the ground voltage to a second positive voltage. The level shifter circuit further includes a first kicker transistor having a first source-drain terminal operable to receive a buffered version of the input signal and having a second source-drain terminal coupled to the output terminal. The first kicker transistor may receive gate signals that turn on the first kicker transistor when the input signal is at the ground voltage and may pull the output terminal to the first positive voltage as the input signal transitions from the ground voltage to the first positive voltage.

Input-output circuit and method of improving input-output signals

One embodiment relates to a programmable output buffer which includes first and second programmable variable-impedance single-ended driver circuits and first and second termination circuits. The first termination circuit is coupled to a first output pin which is driven by the first programmable variable-impedance single-ended driver circuit, and the second termination circuit is coupled to a second output pin which is driven by the second programmable variable-impedance single-ended driver circuit. The first and second termination circuits are programmable to either provide parallel termination for a differential signal or drive single-ended signals with the parallel termination turned off. Other embodiments and features are also disclosed.

Programmable output buffer

Programmable high-speed interface

Growing community of inventors

San Jose, CA, United States of America

Khai Nguyen