Applied Micro Circuits Corporation

Ampere Computing LLC

Keyur Chudgar

Satish Sathe

Vinay Ravuri

Kumar Sankaran

Ankit Jindal

Pranavkumar Sawargaonkar

Shushan Wen

Loc Nhin Ho

Iyappan Subramanian

Rajendra Sadananad Marulkar

Anjan Rudra

Prodyut Hazarika

Perrine Peresse

Tushar Tyagi

A system and method are provided for performing transmission control protocol segmentation on a server on a chip using coprocessors on the server chip. A system processor manages the TCP/IP stack and prepares a large (64 KB) single chunk of data to be sent out via a network interface on the server on a chip. The system software processes this and calls the interface device driver to send the packet out. The device driver, instead of sending the packet out directly on the interface, calls a coprocessor interface and delivers some metadata about the chunk of data to the interface. The coprocessor segments the chunk of data into a maximum transmission unit size associated with the network interface and increments a sequential number field in the header information of each packet before sending the segments to the network interface.

TCP segmentation offload in a server on a chip

Various aspects provide for managing memory in virtual computer system. For example, a system can include a first network node and a second network node. The first network node receives a data packet via a first hardware network controller. The first network node also transmits the data packet over a communication channel via a second hardware network controller in response to a determination that memory data for the data packet is not mapped to the first network node. The second network node receives the data packet via the communication channel and provides the data packet to an operating system associated with the first network node and the second network node.

Managing a data packet for an operating system associated with a multi-node system

Various aspects optimize memory page latency and minimize inter processor interrupts associated with network nodes in a virtual computer system. For example, a system can include a first network node and a second network node. The first network node generates a memory page request in response to an invalid memory access associated with a virtual central processing unit of the first network node. The memory page request includes an identifier for the virtual central processing unit. The second network node receives the memory page request and provides memory data associated with memory page request to the first network node.

Memory page request for optimizing memory page latency associated with network nodes

Various aspects provide for optimizing memory mappings associated with network nodes. For example, a system can include a first network node and a second network node. The first network node generates a memory page request in response to an invalid memory access associated with a virtual central processing unit of the first network node. The second network node receives the memory page request in response to a determination that the second network node comprises a memory space associated with the memory page request. The first network node also maps a memory page associated with the memory page request based on a set of memory page mappings stored by the first network node.

Optimizing memory mapping(s) associated with network nodes

A mapping technique sets coalescing latency values for computing systems that use multiple data queues having a shared base timer. A computing system having at least one receive queue and at least one transmit queue receives user-provided coalescing latency values for the respective queues, and converts these user-provided latencies to coalescing latency hardware register values as well as a base timer register value for the shared base timer. The hardware register values for the coalescing latencies together with the shared base timer register value determine the coalescing latencies for the respective queues. This mapping technique allows a user to conveniently set coalescing latencies for multi-queue processing systems while shielding the user settings from hardware complexity.

Multiple-queue integer coalescing mapping algorithm with shared based time

Various embodiments provide for a system on a chip or a server on a chip that performs flow pinning, where packets or streams of packets are enqueued to specific queues, wherein each queue is associated with a respective core in a multiprocessor/multi-core system or server on a chip. With each stream of packets, or flow, assigned to a particular processor, the server on a chip can process and intake packets from multiple queues from multiple streams from the same single Ethernet interface in parallel. Each of the queues can issue interrupts to their assigned processors, allowing each of the processors to receive packets from their respective queues at the same time. Packet processing speed is therefore increased by receiving and processing packets in parallel for different streams.

Flow pinning in a server on a chip

Various aspects of the present disclosure provide for a system that is able to boot from a variety of media that can be connected to the system, including SPI NOR and SPI NAND memory, universal serial bus ('USB') devices, and devices attached via PCIe and Ethernet interfaces. When the system is powered on, the system processor is held in a reset mode, while a microcontroller in the system identifies an external device to be booted, and then copies a portion of boot code from the external device to an on-chip memory. The microcontroller can then direct the reset vector to the boot code in the on-chip memory and brings the system processor out of reset. The system processor can execute the boot code in-place on the on-chip memory, which initiates the system memory and the second stage boot loader.

System boot with external media

A hardware SATA virtualization system without the need for backend and frontend drivers and native device drivers is disclosed. A lightweight SATA virtualization handler can run on a specialized co-processor and manage requests enqueued by individual guest devices or virtual machines (VMs). The lightweight SATA virtualization handler can also perform the scheduling or queuing of the requests based on performance optimizations to reduce seek time as well as based on the priority of the requests. The specialized co-processor can communicate to an integrated SATA controller through an advanced host controller interface ('AHCI') data structure that is built by the coprocessor and has commands from one or more VMs. Guest devices or guest operating systems can build associated AHCI data structures in memory, which may be on-chip memory or DDR memory.

System and method for SATA virtualization and domain protection

A method is provided for pre-fetching packet data prior to processing. The method accepts a plurality of packets and writes each packet into a memory. A message is derived for each packet, where each message includes a packet descriptor with a pointer to an address of the packet in the memory. Each message is added to a tail of a first-in first-out (FIFO) queue. A pre-fetch module examines a first message, if the first message reaches a first capacity threshold of the FIFO queue. If the first message reaches the first capacity threshold, the pre-fetch module reads a first packet associated with the first message, from the memory, and the first packet is loaded into cache memory. A processor reads the first message from a head of the FIFO queue, and in response to reading the first message, reads the previously loaded first packet from cache memory.

System and method for pre-fetching data based on a FIFO queue of packet messages reaching a first capacity threshold

Various aspects provide large receive offload (LRO) functionality for a system on chip (SoC). A classifier engine is configured to classify one or more network packets received from a data stream as one or more network segments. A first memory is configured to store one or more packet headers associated with the one or more network segments. At least one processor is configured to receive the one or more packet headers and generate a single packet header for the one or more network segments in response to a determination that a gather buffer that stores packet data for the one or more network segments has reached a predetermined size.

Large receive offload functionality for a system on chip

A system and method are provided for evenly distributing central processing unit (CPU) packet processing workloads. The method accepts packets for processing at a port hardware module port interface. The port hardware module supplies the packets to a direct memory access (DMA) engine for storage in system memory. The port hardware module also supplies descriptors to a mailbox. Each descriptor identifies a corresponding packet. The mailbox has a plurality of slots, and loads the descriptors into empty slots. There is a plurality of CPUs, and each CPU fetches descriptors from assigned slots in the mailbox. Then, each CPU processes packets in the system memory in the order in which the associated descriptors are fetched. A load balancing module estimates each CPU workload and reassigns mailbox slots to CPUs in response to unequal CPU workloads.

Packet processing with dynamic load balancing

A hardware-based method is provided for allocating shared resources in a system-on-chip (SoC). The SoC includes a plurality of processors and at least one shared resource, such as an input/output (IO) port or a memory. A queue manager (QM) includes a plurality of input first-in first-out memories (FIFOs) and a plurality of output FIFOs. A first application writes a first request to access the shared resource. A first application programming interface (API) loads the first request at a write pointer of a first input FIFO associated with the first processor. A resource allocator reads the first request from a read pointer of the first input FIFO, generates a first reply, and loads the first reply at a write pointer of a first output FIFO associated with the first processor. The first API supplies the first reply, from a read pointer of the first output FIFO, to the first application.

Method and system for queuing a request by a processor to access a shared resource and granting access in accordance with an embedded lock ID

In a system-on-chip (SoC), a method is provided for partitioning access to resources. A plurality of processors is provided, including a configuration master (CM) processor, a memory, a plurality of OSs, and accessible resources. The method creates a mapping table with a plurality of entries, each entry cross-referencing a range of destination addresses with a domain ID, where each domain ID is associated with a corresponding processor. Access requests to the resource are accepted from the plurality of processors. Each access request includes a domain ID and a destination address. A mapping table is consulted to determine the range of destination addresses associated with the access request domain IDs. The accesses are authorized in response to the access request destination addresses matching the range of destination addresses in the mapping table, and the authorized access requests are sent to the destination addresses of the requested resources.

System and method for partitioning resources in a system-on-chip (SoC)

An operating system (OS) is provided including a hardware-based task scheduler, with a method for managing OS sourced tasks to be performed by a central processing unit (CPU). An OS, partially enabled as software instructions stored in a computer-readable medium and executed by the CPU, generates CPU tasks. The CPU tasks are buffered in a computer-readable task database memory. CPU task IDs associated with the buffered CPU tasks are enqueued in a CPU queue. Subsequently, the CPU dequeues a first task ID from the CPU queue, and accessing a first CPU task from the task database associated with the first CPU task ID. The CPU delivers the first CPU task to the OS. The OS generates the CPU instructions needed to perform the first CPU task, and sends the CPU instructions to the CPU for performance.

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San Jose, CA, United States of America

Keyur Chudgar