Nexflash Technologies, Inc.

Issi/nexflash Technologies, Inc.

Maxim Integrated Products, Inc.

Keyhan Sinai

Paul Jei-Zen Song

Albert M Bergemont

Venkatraman Prabhakar

Low power high density random access memory flash cells and arrays using Fowler Nordheim (FN) tunneling for both programming and erasing. The memory array is divided into sectors, each sector comprising a predetermined number of rows. The bit lines are similarly segmented, each global bit line being selectively connectable to a local bit line for each sector, each local bit line being connected to the drains of all floating gate cells in a respective column of each sector. The sources of all floating gate cells in a respective column of each sector are connected to a local source line for that sector, the local source lines for each sector being controllably connectable to respective global source lines. Consequently all floating gate cells within a column of a sector are connected in parallel, source to source and drain to drain. Representative programming and erase voltages not disturbing other cells are disclosed.

Low power high density random access memory flash cells and arrays

A semiconductor non-volatile memory device is disclosed which is based on the use of Fowler-Nordheim electron tunneling to charge and discharge the isolated gates of the storage cells. The disclosed memory device includes circuitry capable of verifying the threshold level of written storage cells and rewriting only those cells whose threshold is outside a desired threshold range. The disclosed circuit has the further advantage of being able to load data words and verify cell contents simultaneously by utilizing both ends of the bit lines.

Architecture and method for performing page write/verify in a flash

A semiconductor non-volatile memory device is disclosed which is based on the use of Fowler-Nordheim electron tunneling to charge and discharge the isolated gates of the storage cells. Furthermore, the disclosed memory device includes global decoder circuitry capable of passing either positive or negative voltages to a set of global word lines controlling-local decoder circuitry, said local controller circuitry in turn controlling row select lines or local word lines. Each local decoder controls a multiplicity of word lines. The local decoder circuitry is located in physical proximity to specific memory sectors thus resulting in an improved layout of the decoder circuitry and enabling the selection of one of the multiplicity of word lines within said sector by means of electrical control lines. The electrical control lines select one of the multiplicity of rows within a memory sector and deselect all the remaining rows. Logic control circuitry is provided to control the logic of the local row decoders.

Local row decoder and associated control logic for fowler-nordheim

An erase state machine controls the process of erasing all the memory cells in a selected sector of a flash memory array. The erase state machine includes a sequence of states for controlling generation of high positive and negative voltages, and application of the high positive voltage to all word lines in the selected sector and application of the high negative voltage to the source nodes of all memory cells in the selected sector. A sequence of two discharge states are used to discharge the high voltages from the word lines and source nodes. If an erase operation is aborted while high voltages are being generated, the erase state machine asynchronously transitions to the first of the two discharge states, and then transitions to the second discharge state and then back to a final inactive state during successive state machine clock cycles. Further, the erase state machine simultaneously checks all the cells in the selected sector to see if they are fully erased, without having to use a repeating loop of states for that purpose. The program state machine controls the programming of one page of flash memory cells. It enables the use of N/2.sup.k programming bit latches in the memory array, instead of a full set of N programming bit latches, where N is the number of columns in the memory array and k is a positive integer, thereby alleviating the space constraints normally imposed on programming bit latches in flash memory devices.

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Santa Clara, CA, United States of America

Keyhan Sinai