Lattice Semiconductor Corporation

Kexin Luo

Yu Shen

Kai Zhou

Qiming Wu

Kai Lei

Zhi Wu

Min-Kyu Kim

Gijung Ahn

Fei Song

Xiaofeng Wang

Inyeol Lee

Rui Yin

Shinje Tahk

Yibin Fu

Fangqing Chu

Xiaozhi Lin

Yan Rui

Shaoyong Lu

Shengguo Cao

Lingfen Yue

Fangquing Chu

Jie Yuan

Guofu Peng

Huaizhou Yang

Example embodiments of the present disclosure relate to a line driver apparatus. In some example embodiments, an apparatus is provided. The apparatus includes a capacitive feed-through module and a driving module. The capacitive feed-through module includes a first pre-driver operable to receive input differential signals and delayed signals of the input differential signals, generate first drive signals from the input differential signals and the delayed signals, and equalize the first drive signals. The capacitive feed-through module also includes a capacitance reducing module arranged between the first pre-driver and transmission lines and operable to reduce parasitic capacitance at the transmission lines in response to the first drive signals. The driving module is coupled to the transmission lines and operable to generate output differential signals from the input differential signals for transmission on the transmission lines.

Line driver apparatus with combined feed-through capacitance and feed-forward equalization

A voltage controlled oscillator (VCO) is disclosed. The VCO includes an amplifier that receives a control signal and a feedback signal and generates an amplified output signal based on the difference between the control signal and the feedback signal. The VCO also includes circuitry to generate an oscillating output signal based on the amplifier output signal. Additionally, the VCO includes a feedback amplifier that generates the feedback signal based on the output of the amplifier. The feedback amplifier includes a first resistor connected in parallel with a second resistor, the second resistor having an adjustable resistance.

Spectrum shaping voltage to current converter

Embodiments relate to a voltage oscillator (VCO) that uses a replica bias circuit to generate a cascode bias voltage. The VCO generate an output periodic signal having a frequency and phase that is less or not susceptible to voltage swings by using a bias voltage generated in a replica bias circuit that replicates a voltage-to-current converter in the VOC. The bias voltage is generated and regulated according to a power supply voltage that supplies power to the VCO to account for voltage variations in the power supply voltage.

Replica cascode bias voltage-controlled oscillators

A method that calibrates a device for echo cancellation and a device with calibration for echo cancellation are provided. Devices may be calibrated such that the echo residual error is less than a threshold determined by the calibration accuracy. Non-ideal factors such as mismatch may be eliminated during calibration.

Calibration for echo cancellation in a full duplex communication system

Embodiments relate to type-I PLLs that do not lock at a sub-harmonic frequency of a reference clock signal by controlling timing of charging or discharging of one or more capacitors in the PLLs. A phase frequency detector (PFD) of a type-I PLL can prevent sub-harmonic locking by generating a clear output signal to cause a sampling capacitor of PLL's loop filter to discharge only during a time period when the sampling capacitor is not being charged. For example, the PFD can include a gating element to control the time during which the clear output signal is generated. By ensuring that the sampling capacitor is not discharged during a time period while it is being charged, the PLL's voltage-controlled oscillator is controlled to oscillate at an intended frequency rather than at a sub-harmonic of the intended frequency.

Phase locked loop with sub-harmonic locking prevention functionality

Embodiments describe techniques for utilizing fractional-N phase locked loops (PLL). Some embodiments describe a fractional-divider based fractional-N PLL for a spread spectrum clock (SSC) generator that utilizes phase average techniques to suppress phase interpolator nonlinearity. Some embodiments describe a fractional-N PLL based on fractional dividers with hybrid finite impulse response (FIR) filtering. Some embodiments describe a small size and low power divider for a hybrid FIR fractional-N PLL.

Techniques for fractional-N phase locked loops

Embodiments of the invention are generally directed to a linear regulator with improved power supply ripple rejection. An embodiment of an apparatus includes an linear regulator to receive a system power supply and to generate a regulated power supply; a first voltage reference generator to generate a first voltage reference for the linear regulator; a second voltage reference generator to generate a second voltage reference for the linear regulator; and a voltage reference and power switcher. In some embodiments, the voltage reference and power switcher is to switch a voltage reference for the linear regulator from the first voltage reference to the second voltage reference and is to switch a part of a power supply for the linear regulator from the system power supply to the regulated power supply.

Linear regulator with improved power supply ripple rejection

Embodiments relate to successive approximation register (SAR)-based analog-to-digital converters (ADCs) that increase a time frame allocated for the settling of capacitors in a digital-to-analog converter (DAC) capacitor network by feeding a comparator output signal to the DAC to begin DAC capacitor settling before the comparator output is latched by a clock signal at a latching time. The SAR ADC can include a window circuit that provides the comparator output directly from the comparator to the DAC before the latching time of the comparator. After the latching time, the latched version of the comparator output is provided to the DAC capacitor. By providing the capacitor output to the DAC capacitor before latching, DAC capacitor can settle earlier compared to an SAR ADC where DAC capacitor settling begins after the latching time of the comparator.

Successive approximation register-based analog-to-digital converter with increased time frame for digital-to-analog capacitor settling

Embodiments of the invention are generally directed to a line driver with separate pre-driver for feed-through capacitance. An embodiment of an apparatus includes a differential pair of transistors to generate an output signal on a first output node and a second output node; a pass-through capacitance coupled with the first output node and the second output node; a first pre-driver to drive an input signal for the differential transistors; and a second pre-driver to drive the input signal for the pass-through capacitance.

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Shanghai, China

Kexin Luo