Wisconsin Alumni Research Foundation

Kewal Saluja

Parameswaran Ramanathan

Spencer Millican

Dong Hyun Baik

Kyuchull Kim

A system for creating protected functional descriptions of integrated circuits provides encrypted gate delay information preventing deduction of gate function from gate delay but allowing simulation of the integrated circuit with accurate propagation delay calculation. Individual gate delay values may be modified so that they obscure actual gate delays but so that the modified individual gate delays total to equal the actual cumulative gate delay along a given data propagation path.

Encrypted digital circuit description allowing signal delay simulation

A system for creating protected functional descriptions of integrated circuits provides an encrypted functional description that allows the integrated circuit to be simulated with respect to producing outputs for given sets of inputs without identification of the constituent components of the integrated circuit such as the logical gates making up the integrated circuit. The encrypted functional description may include encrypted truth-tables describing the generic gates of the integrated circuit, the encrypted truth-tables securing the function of each logical gate by including multiple redundant table entries mapped to alias values of Boolean logical states and erroneous table entries.

Encrypted digital circuit description allowing circuit simulation

Wrapper cells for simultaneous testing of parent functional elements and child functional elements in a hierarchical SoC (System on Chip) provide a substantially reduced integrated circuit footprint by eliminating a multiplexer and providing simpler interconnections. Identical wrapper cells may be used for input and output data lines reducing the cost of the cell library.

Wrapper cell for hierarchical system on chip testing

A scan cell is described for testing an integrated circuit. The scan cell may include circuitry adapted to operate in a non-test mode as a storage element and adapted to operate as a static random access memory (SRAM) cell in a test mode. For example, the circuitry may include one or more pass transistors and a flip flop. The scan cell may be one of a plurality of addressable scan cells in one or more grids for testing the integrated circuit. For example, the scan cells may be arranged in a single grid or may be partitioned into two or more grids. The scan cell may be used for reliability testing or for performance testing. The PRAS cell for performance testing may be staged, with a first pattern applied and then a second pattern applied. For example, one section of the scan cell may operate using a clock cycle of &#x3a6;and another section of the PRAS cell may operate using a clock cycle of &#x3a6;which is different from &#x3a6;.

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Madison, WI, United States of America

Kewal Saluja