International Business Machines Corporation

Kevin William McCullen

Sebastian Theodore Ventrone

Stephen William Mahin

Daniel Mathew Wronski

A computer processor architecture which employs an on-chip cache macro and an on-chip memory map is described. The memory map contains indicia of the cachability of different segments of off-chip memory, preferably along with an indication of the read/write status of each off-chip memory segment. A processor generated address signal is then compared on-chip with the memory map to ascertain whether the generated signal falls within a segment which is cachable or uncachable and which is read-only or read/write.

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Jericho, VT, United States of America

Kevin William McCullen