International Business Machines Corporation

Cadence Design Systems, Inc.

Kevin William McCauley

Richard Frank Rizzolo

Franco Motika

William Vincent Huott

Peilin Song

Mary Prilotski Kusko

Donald Lawrence Wheater

Salim Ahmed Shah

Joseph Michael Swenton

Bryan J Robbins

Pamela Sue Gillis

Visweswara Rao Kodali

Johnny James LeBlanc

Ronald J Prilik

Ulrich Baur

Francis Woytowich

Richard Gabrielson

For each logic gate in a logic circuit, all paths containing the gate are determined and the paths are classified by their length between each of the input or launch SRLs and each output or capture SRL. The paths are assigned a single threshold value and then divided into two groups in accordance with their path length classification relative to the threshold value with all paths in each group treated as a single path. Pseudo random LBIST patterns are then simulated using standard LBIST tool. When a fault associated with a logic gate is detected by a capture SRL of a path with a length above the threshold, the fault is viewed as tested and marked off from the fault list. When a fault is detected in any path that is below the threshold, it is not marked off and testing of the fault continues until testing patterns for all the paths of the group falling below the threshold value are simulated. When all the faults paths of the group falling below the threshold have been tested, a separate determined test generation program is activated. In the generated test, the fault is forced to propagate through the longest path above the threshold value.

Random path delay testing methodology

A method to improve the testability and analysis of a hierarchical semiconductor chip design formed from a plurality of macros, each macro identifying a particular portion of a semiconductor chip design. This method includes providing a first macro netlist that identifies a logical description of a first portion of the semiconductor chip design and performing RPT analysis on the first macro netlist. The method also includes providing a second macro netlist identifying a logical description of a second portion of the semiconductor chip design and performing an RPT analysis on the second macro netlist. The first macro netlist is combined with the second macro netlist and an RPT analysis is performed on the combination of the first and second macro netlists.

Method to improve a testability analysis of a hierarchical design

A method and implementing system is provided in which input signal specifications, element internal delays and output loads, for each element in a circuit design, are utilized in an iterative processing engine to objectively determine and provide a timing rule database for a circuit being designed. A schematic database netlist is run through a test model converter program to provide a test model database at a gate level for the test model design circuit. These data are processed by a designer through a workstation GUI and the result is applied to an I/O design testing function. The results of the I/O design testing function include a listing of patterns of input combinations which are needed to get listed outputs. The GUI prepares a sequence of stimuli to test the circuit with a timing simulator. Based on the output response of the timing simulator, delay relationships under various input and output load conditions are compiled.

Analyzing CMOS circuit delay

A method and apparatus for testing a semiconductor chip includes providing the semiconductor chip with a common input/output (I/O) or bidirectional I/O pad. The I/O pad is electrically coupled to an off-chip driver (OCD) and an off-chip receiver (OCR). The OCD, I/O pad, and OCR are combined in a common input/output (CIO) or bidirectional I/O configuration. The I/O pad is effectively open circuited by an external tester and a performance parameter of the IO circuits connected to the open circuited pad is tested.

Self-timed AC CIO wrap method and apparatus

Growing community of inventors

Greene, NY, United States of America

Kevin William McCauley