International Business Machines Corporation

Invecas, Inc.

Globalfoundries Inc.

Synopsys, Inc.

Globalfoundries U.S. 2 LLC

Kevin William Gorman

Michael Richard Ouellette

Michael Anthony Ziegerhofer

Darren Lane Anand

Emory D Keller

John Edward Barth, Jr

Krishnendu Mondal

Kiran K Narayan

Valerie Hornbeck Chickanosky

Harold Pilo

George Maria Braceras

Aravindan J Busi

Deepak I Hanagandi

Suzanne Granato

Thomas Chadwick

Nancy Pratt

Michael R Nelms

John Atkinson Fifield

Rohit Pradeep Shetty

Saravanan Sethuraman

Albert Manhee Chu

David E Lackey

Donald Lawrence Wheater

Jeffrey H Dreibelbis

Patrick Edward Perry

Daryl Michael Seitzer

Steven Michael Eustis

Ronald A Piro

Thomas W Wyckoff

Toshiaki Kirihata

Igor Arsovski

Wayne Frederick Ellis

Paul Christian Parries

Matthew R Wordeman

Steven Frederick Oakland

Dale E Pontius

Gregory J Fredeman

John Robert Goss

Robert Maurice Houle

Mark David Jacunski

Michael Thomas Fragano

Troy Joseph Perry

Nancy H Pratt

Alan D Norris

Jonathan R Fales

Derek H Leu

Michael A Roberge

Steven Joseph Urish

Kelly A Ockunzzi

Valarie H Chickanosky

Aaron J Cummings

George M Belansek

Michael R Oullette

Adrian J Paparelli

A memory bypass circuit for a memory device comprises: a word line disable circuit; a read and write activation circuit; an internal clock generator; and a write data input circuit. The word line disable circuit is coupled to a word line of the memory device for disabling a write function to the word line. The read and write activation circuit is coupled to the memory device for reading and writing of input data. The internal clock generator is coupled to the word line disable circuit and the read/write activation circuit. The write data input circuit is coupled to a write driver of the memory device for providing write data.

Memory bypass function for a memory

A serial arbitration for memory diagnostics and methods thereof are provided. The method includes running a built-in-self-test (BIST) on a plurality of memories in parallel. The method further includes, upon detecting a failing memory of the plurality of memories, triggering arbitration logic to shift data of the failing memory to a chip pad.

Arbitration for memory diagnostics

A memory built-in self test ('BIST') system comprises: a controller; a single port memory engine coupled to one or more single port memories; and a non-single port memory engine coupled to one or more non-single port memories. The controller receives operation codes ('op-codes') for testing a plurality of memory types. An output of the controller is coupled to inputs of the single port memory engine and the non-single port memory engine. The controller generates test instructions based on the received op-codes. The single port memory engine and the non-single port memory engine interpret the test instructions to test the one or more single port memories and the one or more non-single port memories.

Memory built-in self test system

A memory diagnostic system comprises a test engine and a miscompare logic. The test engine provides test instructions with expected data to a memory under test ('MUT'). The MUT processes such test patterns and outputs the results of such test patterns as stored data. The miscompare logic has local miscompare logics and a global miscompare logic. Each of the local miscompare logics compares a predefined range of bits of the expected data with a corresponding predefined range of bits of the stored data. One or more miscompare flags are generated for one or more miscompares determined by the local miscompare logics. The global miscompare logic monitors the one or more miscompare flags. When a total number of the miscompare flags exceeds a threshold number, the global miscompare logic generates a pause signal to the local miscompare logics to capture a current state of the local miscompare logics.

Diagnostics for a memory device

A fuse controller comprises: a fuse bay, a bus, an engine, and an interface. The fuse bay stores repair and setting information for a plurality of fuse domains in a linked-list data structure. The engine manages the linked-list data structure. The engine also is coupled to the fuse domains via the bus. The interface is coupled to the engine and receives commands and data for operating the engine.

Multi-domain fuse management

Aspects of the invention provide for reducing BIST test time for a memory of an IC chip. In one embodiment, a BIST architecture for reducing BIST test time of a memory for an integrated circuit (IC) chip, the architecture comprising: a pair of latches for receiving bursts of data from a memory; a first compression stage for receiving a burst of data and compressing the burst of data into a plurality of latches; a second compression stage for comparing the compressed bursts of data with expected data; and a logic gate for determining whether there is a fail in the burst of data.

Built-in-self-test (BIST) test time reduction

Systems and methods are provided for reusing existing test structures and techniques used to test memory data to also test error correction code logic surrounding the memories. A method includes testing a memory of a computing system with an error code correction (ECC) logic block bypassed and a first data pattern applied. The method further includes testing the memory with the ECC logic block enabled and a second data pattern applied. The method also includes testing the memory with the ECC logic block enabled and the first data pattern applied.

Memory test with in-line error correction code logic to test memory data and test the error correction code logic surrounding the memories

Logic and methods for diagnostic testing of memory and, more particularly, auto shift of failing memory diagnostics data using pattern detection are disclosed. The method includes detecting fails in the memory during a built in self test (BIST) pattern. The method further includes passing the fail information to a tester through a diagnostic pin. The method further includes pausing shift operations when it is determined that the shifting of the fail information is complete for the detected fail.

Fast auto shift of failing memory diagnostics data using pattern detection

A read only memory (ROM) with redundancy and methods of use are provided. The ROM with redundancy includes a programmable array coupled to a repair circuit having one or more redundant repairs. The one or more redundant repairs include a word address match logic block, a data I/O address, and a tri-state buffer. The word address match logic block is provided to the tri-state buffer as a control input and the data I/O address is provided to the tri-state buffer as an input. An output of the tri-state buffer of each redundant repair is provided as a first input to one or more logic devices. One or more data outputs of a ROM bit cell array is provided as a second input to a respective one of the one or more logic devices.

Read only memory (ROM) with redundancy

Memory test with in-line error correction code logic

Structures, methods, and systems for designing and verifying integrated circuits including redundant logic blocks are provided. An integrated circuit includes selection logic and selectable logic blocks that are individually controllable by the selection logic. The selectable logic blocks include respective instances of a redundant logic block, and respective instances of an interface logic block that selectively disable the redundant logic blocks in the integrated circuit.

Verifying partial good voltage island structures

Each register in each built-in self-test (BIST) controller contains a BIST controller-specific start count value that is different from at least one other BIST controller-specific start count. A test controller provides a start command simultaneously to all the BIST controllers. This causes each of the BIST controllers to simultaneously begin a countdown of the BIST controller-specific start count values, using a counter. Each of the BIST controllers starts a test procedure in a corresponding BIST domain when the countdown completes (in the corresponding BIST controller). Thus, the test procedure starts at different times in at least two of the BIST domains based on the difference of the BIST controller-specific start count values in the different registers. Further, during the test procedure, each stagger controller can stagger the start of each BIST engine within the corresponding BIST domain to which the stagger controller is connected.

Staggered start of BIST controllers and BIST engines

Aspects of the invention provide a bypass structure for a memory device for reducing unknown test values, and a related method. In one embodiment, a bypass structure for a memory device is disclosed. The bypass structure includes: a logic gate configured to receive a test signal and a clock signal; and an output latch configured to receive an output of the logic gate, an output of the memory device, and a bypass data signal, wherein the output latch is configured to hold the bypass data signal and bypass the output of the memory device in response to asserting the test signal, such that unknown data from the output of the memory device is bypassed.

Bypass structure for a memory device and method to reduce unknown test values

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Fairfax, VT, United States of America

Kevin William Gorman