Nvidia Corporation

Kevin Wilder

Tezaswi Raja

Amit D Sanghani

Shantanu Sarangi

Rajeshwaran Selvanesan

Milind Bhaiyyasaheb Sonawane

Karthikeyan Natarajan

Narayan Kulshrestha

Mahmut Yilmaz

Madhukiran V Swarna

Jonathon E Colburn

Divya Ramakrishnan

Benjamin Faulkner

Sailendra Chadalavda

Aniket Naik

Pavan Kumar Datla Jagannadha

Ramachandiran V

Ka Yun Lee

Anand Shanmugam Sundararajan

Dheepakkumaran Jayaraman

Daniel Rodriguez

Raj Jayakar

Fei (Walter) Li

Brian Smith

Various embodiments include a computer memory system that dynamically adjusts a memory device performance feature, such as dynamic assist control, dynamic turbo mode, and/or the like, to improve the performance of memory devices in the memory system. The memory system enables or disables the memory device performance feature based on the operating voltage relative to a threshold voltage. If the operating voltage crosses the threshold voltage in one direction, then the memory device system enables the memory device performance feature. If the operating voltage crosses the threshold voltage in another direction, then the memory system disables the memory device performance feature. Various techniques enable the memory device performance feature to be employed even with complex integrated circuits that may include tens of thousands of devices that employ the memory device performance feature.

System level hardware mechanisms for dynamic assist control

Systems and techniques for improving the performance of circuits while adapting to dynamic voltage drops caused by the execution of noisy instructions (e.g. high power consuming instructions) are provided. The performance is improved by slowing down the frequency of operation selectively for types of noisy instructions. An example technique controls a clock by detecting an instruction of a predetermined noisy type that is predicted to have a predefined noise characteristic (e.g. a high level of noise generated on the voltage rails of a circuit due to greater amount of current drawn by the instruction), and, responsive to the detecting, deceasing a frequency of the clock. The detecting occurs before execution of the instruction. The changing of the frequency in accordance with instruction type enables the circuits to be operated at high frequencies even if some of the workloads include instructions for which the frequency of operation is slowed down.

Techniques for configuring a processor to execute instructions efficiently

Granular dynamic test systems and methods facilitate efficient and effective timing of test operations. In one embodiment, a chip test system comprises: a first test partition operable to perform test operations based upon a first local test clock signal; a second test partition operable to perform test operations based upon a second local test clock signal; and a centralized controller configured to coordinate testing between the plurality of test partitions, wherein the coordination includes managing communication of test information between the plurality of test partitions and external pins. In one exemplary implementation, a trigger edge of the first local test clock signal is staggered with respect to a trigger edge of the second local test clock signal, wherein the stagger is coordinated to mitigate power consumption by test operations in the first test partition and test operations in the second test partition.

Independent test partition clock coordination across multiple test partitions

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Menlo Park, CA, United States of America

Kevin Wilder