Applied Micro Circuits Corporation

Qualcomm Incorporated

University of California

Kevin Warren James

Kenneth Yun

Kirk Alvin Miller

Michael Hellmer

George Bendak

Viet Linh Do

Sushil Kumar Singh

Jianfeng Shi

John David Huber

David Thomas Dougherty

John Calvin Leung

A system and method are provided for fairly distributing grants for access to switch outputs, through crossbars, between switch input channels. Crossbars are granted access between specified switch inputs and switch outputs, and the least recently used input channels are associated with selected switch outputs. A history of the previous channel transaction is maintained for each switch output, and channels are nominated in a rotation through a priority channel list. The present invention bid grant algorithm permits information packets to be transferred across a switch in the time between a bid submission and a bid grant.

System and method for reevaluating granted arbitrated bids

System and method for granting arbitrated bids in the switching of information

A system and method are provided for resynchronizing backplane link management credit counters in a packet communications switch fabric. The method comprises: at an input port card ingress port, accepting information packets including cells and cell headers with destination information; modifying the destination information in the received cell headers; routing information packets between the input port card and output port cards on backplane data links through an intervening crossbar; at the input port card, maintaining a credit counter for each output port card channel; decrementing the counter in response to transmitting cells from the input port card; generating credits in response to transmitting cells from an output port card channel; sending the generated credits to increment the counter, using the modified destination information; and, using the generated credit flow to resynchronize the credit counter.

System and method for synchronizing switch fabric backplane link management credit counters

A credit-based system and method are provided for managing backplane traffic flow in a packet communications switch fabric. The method comprises: accepting information packets including cells and cell headers with destination information; modifying the destination information in the received cell headers; routing information packets between an input port card and output port cards on backplane data links through an intervening crossbar; at the input port card, maintaining a credit counter for each output port card channel; decrementing the counter in response to transmitting cells from the input port card; generating credits in response to transmitting cells from an output port card channel; and, using modified destination information, sending the generated credits to increment the counter. In some aspects, modifying the destination information in the received packet headers includes: extracting the output port card termination from the card field; and, inserting the input port card source in the card field.

Switch fabric backplane flow management using credit-based flow control

A system and method are provided for cut-through packet routing in a packet communications switch fabric. The method comprises: accepting information packets addressed to a plurality of output port card egress ports at an input port card ingress port; routing information packets between port cards on backplane data links through an intervening crossbar; maintaining a credit counter for each port card egress destination, at the input port card; decrementing the counter in response to transmitting cells in a packet from the input port card; and, incrementing the counter in response to transmitting cells from the packet at the output port card. In some aspects of the method, accepting information includes buffering the packets in an ingress memory subsystem (iMS). Routing information includes the iMS transmitting buffered packets on a selected backplane data link. Decrementing the counter includes the iMS communicating with the iPQ in response to transmitting a cell.

Minimum latency cut-through switch fabric

A system and method have been provided for prioritizing queued information packets having a variable number of cells. A simultaneous deficit round robin (DRR) analysis occurs in the course of several selection cycles. Each queue has an associated increment value. The packet lengths in each queue are simultaneously compared to an accumulation total in every selection cycle. If all the packets have lengths greater than their corresponding accumulation totals, each accumulation total is incremented and the selection process is repeated. If one of the information packets has a number of cells less than, or equal to its corresponding accumulation total, it is selected. In case multiple information packets are eligible, a variety of selection criteria can be used to break a tie. For example, the eligible information packet with the highest class of service (COS) can be selected. The information packet is completed transferred before another selection process is begun.

System and method for simultaneous deficit round robin prioritization

A system and method have been provided for hierarchically arbitrating in a broadband information switching network. The method promotes the fair and efficient distribution of information packets across the switch fabric that ultimately permits the switch to maximally match information packets to switch output addresses, at faster rates and higher throughput. The method comprises: accepting variably sized information packets at a plurality of switch inputs, that address a plurality of switch outputs; at each switch input, queuing the information packets into a plurality of queues; parsing the information packets into units of one cell; simultaneously arbitrating between each switch output and a plurality of available switch inputs, where an available input is defined to have at least one queue with an information packet addressing that particular switch output; selecting a queue; locking the link between switch inputs and switch outputs; and, transferring information packets across the links in units of one cell per master decision cycle.

System and method for hierarchical switching

The cell switching architecture of the present invention uses at least one earliest deadline first (EDF) queue for each of the output ports in a cell switch so that no two output ports have a common earliest-deadline-first queue. Cells are arranged in each EDF queue according to deadline, but each EDF queue only contains cells for a single destination output port. Each input port also has an input queue with an EDF queue for each of the output ports, and each EDF queue arranges the cells for a single output port. Many equivalent cells may be represented by a single EDF queue entry, enabling large buffer capacity to be supported by small EDF queues. The architecture provides a method for switching cells between a plurality of input ports and a plurality of output ports. Cells are accepted from input ports into a plurality of corresponding input queues. Cells are sorted into groups according to the destination output port such that each group includes cells destined for a single output port. Within each input queue, at least one group is formed for every output port for which cells are available. Cells are arranged, within each group, according to deadline. By means of a central arbiter, output ports then choose cells to read in a read cycle from the earliest deadline cells in their corresponding cell groups in the input queues. An efficient method is used to select cells with the earliest deadlines.

Growing community of inventors

San Diego, CA, United States of America

Kevin Warren James