Intel Corporation

Hewlett-packard Development Company, L.p.

Kevin W Rudd

Dale Calvin Morris

Tin-Fook Ngai

Allan Douglas Knies

James M Hull

Udo Walterscheidt

A system and method for determine which threads to execute at a given time in a multi-threaded computer system. A thread prioritizer determines execution fairness between pairs of potentially executing threads. A switch enabler determines forward progress of each executing thread. The resulting indicators from the thread prioritizer and switch enabler may aid in the determination of whether or not to switch a particular potentially executing thread into execution resources.

Method and apparatus for ensuring fairness and forward progress when executing multiple threads of execution

Methods and apparatus for enforcing instruction-cache coherence are described herein. In an example method, a memory region of an instruction cache is initialized to form an initialized memory region prior to generating new code associated with the initialized memory region. Coherence code associated with the initialized memory region is generated. The new code associated with the initialized memory is generated. At least one of the new code and the coherence code is executed. Other embodiments may be described and claimed.

Methods and apparatus for enforcing instruction-cache coherence

A method and apparatus for enabling the speculative forking of a speculative thread is disclosed. In one embodiment, a speculative fork instruction is conditioned by the results of a fork predictor. The fork predictor may issue predictions as to whether or not a speculative thread would execute desirably. The fork predictor may be implemented as a modified branch predictor circuit, and may have execution history updates entered by a determination of whether or not the execution of a speculative thread was or would have been desirable.

Method and apparatus for prediction for fork and join instructions in speculative execution

A processor comprising a feature indicator associated with at least one of a first sequence of one or more instructions, a first register, a second register, and an execution core is provided. The execution core is configured to execute a second instruction to cause the first register to be set to a first value using the feature indicator and to cause the second register to be set to a second value using the feature indicator. The execution core is configured to execute the first sequence of one or more instructions to cause a function to be performed in response to the first value in the first register indicating a true condition, and the execution core is configured to execute a second sequence of one or more instructions to cause the function to be performed in response to the second value in the second register indicating the true condition.

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Portland, OR, United States of America

Kevin W Rudd