Altera Corporation

Kevin W Mai

Jakob Raymond Jones

Jeffrey Fox

Vishwas Tumkur Vijayendra

Yury Markovskiy

Nikolaos Liveris

A method for designing a system on a target device includes generating a timing netlist that reflects timing delays and timing relationships of a base configuration of a block in the system and a target configuration of the block in the system, wherein the base configuration of the block and the target configuration of the block implement different functionalities, and performing synthesis, placement, and routing on the system in response to the timing netlist.

Method and apparatus for performing a single pass compilation for systems with dynamically reconfigurable logic blocks

Methods for designing and developing models for simulating the behavior of clock signals and in particular those generated by phase-locked loop (PLL) circuits are provided. The clock period of a phase-locked loop circuit's variable frequency oscillator signal may be modeled by combining the inverse of the oscillator frequency rounded up to the simulation time scale with the inverse rounded down to the simulation time scale. The variable frequency oscillator signal may further be synchronized with a reference clock signal at a rate determined by the relationship between the reference clock signal and the variable frequency oscillator signal. A parameter may indicate a target range for the deviation between the two signals and a runtime monitor may be used together with the parameter setting to decide whether synchronization is required and make the appropriate adjustments.

Parameterizable method for simulating PLL behavior

Circuits, methods, and apparatus are directed to sharing input and output functionality. A timing circuit usable for input and output functionality may be combined with another timing circuit to provide additional input/output functionality or to reduce the number of circuit elements for input/output functionality. For example, two timing circuits may be used to provide double data-rate input while still providing output functionality, or vice versa. Two timing circuits may also provide output that is timed and gated with an output enable signal.

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Kevin W Mai