International Business Machines Corporation

Kevin W Kark

K Paul Muller

Liyong Wang

William Vincent Huott

Warren Edward Maule

Kevin Charles Gower

Mark William Kellogg

David S Wolpert

John Greg Massey

David L Rude

William Wu Shen

George C Wellwood

Kenneth Y Chan

Pak-kin Mak

Thomas J Knips

Luiz Carlos Alves

William J Clarke

Christopher Raymond Conklin

Russell W Lavallee

Carl B Ford, Iii

Frank David Ferraiolo

Timothy Jay Dell

Bruce G Hazelzet

Uma Srinivasan

Walter Heinrich Lipponer

Roger A Rippens

Henry Chin

Udo Wille

Hartmut Ulland

Donald J Swietek

Charles D Holtz

Judy S Chen Johnson

Pamela Antal

Judy Shan-Shan Chen Johnson

Pattern recognition is used to proactively treat defects of repeating circuit topologies. A component of a computing environment is monitored for failures. The component includes one or more repeating circuit topologies. A determination is made as to whether a new failure within a repeating circuit topology of the one or more repeating circuit topologies has occurred within a predefined amount of time from a previous failure matching a selected pattern, in which the selected pattern indicates a non-contiguous growing defect. Based on determining the new failure has occurred within the predefined amount of time from the previous failure matching the selected pattern, corrective action for the component is proactively taken.

Pattern recognition for proactive treatment of non-contiguous growing defects

Embodiments relate to built-in testing of an unused element on a chip. An aspect includes concurrently performing on a chip comprising a plurality of chip elements comprising a plurality of active elements, each active element enabled to perform a respective function, and at least one unused element that is disabled from performing the respective function and configured to be selectively enabled as an active element, the respective functions of the respective active elements and a built-in self test (BIST) test of the at least one unused element. Another aspect includes inputting an input test pattern to the unused element. Another aspect includes receiving an output test pattern based on the input test pattern from the unused element. Another aspect includes comparing the input test pattern to the output test pattern. Another aspect includes determining whether the unused element passed or failed the testing based on the comparison.

Built-in testing of unused element on chip

A system for providing error detection or correction on a data bus includes one or more caches coupled to a central processing unit and to a hub by one or more buses. The system also includes a plurality of arrays, each array disposed on one of the buses. Each of the arrays includes a plurality of storage cells disposed in an insensitive direction and an error control mechanism configured to detect an error in the plurality of storage cells.

Error protection for a data bus

A method for providing error detection and/or correction to an array of storage cells includes determining a sensitive direction and an insensitive direction of the storage cells and adding a first error control mechanism to the array of storage cells in the insensitive direction. The method also includes adding a second error control mechanism to the array of storage cells in the sensitive direction. The second error control mechanism has a higher Hamming distance than the first error control mechanism.

Error protection for integrated circuits

A method for configuring the placement of a plurality of storage cells on an integrated circuit includes grouping the plurality of storage cells into a plurality of words, where each of the plurality of words is protected by an error control mechanism. The method also includes placing each of the storage cells on the integrated circuit such that a distance between any two of the storage cells belonging to one of the plurality of words is greater than a minimum distance. The minimum distance is configured such that a probability of any of the plurality of words experiencing multiple radiation induced errors is below a threshold value.

Placement of storage cells on an integrated circuit

A method for adding error detection, or error detection combined with error correction, to a plurality of register banks includes grouping the plurality of register banks into an array. The method also includes adding a first error control mechanism to the array in a first direction and adding a second error control mechanism to the array in a second direction. The method further includes adding a product code to the array, the product code including applying the second error control mechanism to a plurality of bits of the first error control mechanism.

Shared error protection for register banks

A memory subsystem with positional read data latency that includes one or more memory modules, a memory controller and one or more memory busses is provided. The memory controller includes instructions for providing positional read data latency. The memory modules and the memory controller are interconnected via the memory busses.

Memory subsystem with positional read data latency

A method of regulating power for multi-node computer system components has a closed-ring path that links all the power governors and circulating in the ring is a system power number that represents the power consumption of the entire system. Meanwhile, all the governors keep counting its local power consumption. Each time the number passes a governor, the governor will add its local count onto this number, store this number for future usage, and reset its local count. When the new number returns back to the same power governor, the governor will subtract the new number with its stored number to calculate the overall system power usage within a number circulation period. The system power number overflow problem is also detected with a counter if the incoming number is smaller then the number previously stored. The counter whose counting capacity is greater than the maximum system power usage on all the nodes within a number circulation period. A single number transfer mode and multiple number transfer mode and heterogeneous multi-node components which could have different power usage configurations are employed.

System for circulating power usage information on a closed ring communication path with multi-node computer system

A self test function in the Memory Controller is utilized to generate unique and continuous data patterns for each of the words which are stored into two consecutive DRAM addresses in two spaced store operations. The self test function then generates fetch commands to read back the unique data patterns from the two DRAM addresses. In the fetch operations, the data transmission for each operation and between both operations is contiguous (no gaps). A self test data comparison function is then used to compare these fetched data words to data patterns which are generated from the self test data generator. Bit error counters from the memory controller keeps track of any miscompares. By reading out a unique signature from these bit counters, it can be determined whether the store path data are misaligned early or late or correct and/or the fetch path data are misaligned early or late or correct. In addition, the exact number of cycles the data are early or late is known. Based on the last results, either or both the store and/or fetch data path capture window parameters are adjusted to correct or early or late bit position.

Data capture window synchronizing method for generating data bit sequences and adjusting capture window on parallel data paths

A packetized cascade memory system including a plurality of memory assemblies, a memory bus including multiple segments, a bus repeater module and a segment level sparing module. The bus repeater module is in communication with two or more of the memory assemblies via the memory bus. The segment level sparing module provides segment level sparing for the communication bus upon segment failure.

System, method and storage medium for providing a serialized memory interface with a bus repeater

A method for regulating system power using a power governor for DRAM in a multi-node computer system regulating memory power consumption of an entire computer system employs a closed ring that connects all the power governors within the system to enable them to work in concert so that each of the power governors has the knowledge of memory activities within the entire system. They then control and limit the memory usage based on a true overall measurement instead of just local measurement. Each nodal power governor has memory command counter, ring number receiver, ring number transmitter, governor activation controller, and memory traffic controller. Each nodal power governor counts the weight of memory command. The degree of limiting actual memory activities can be programmed when the governor is active. Besides, the command priorities can be adjusted in activation too. A hybrid ring structure can be employed with a nodal power structure to achieve the fastest number circulation speed economically.

System for regulating system power by controlling memory usage based on an overall system power measurement

Storage protection keys and system data share the same physical storage. The key region is dynamically relocatable by firmware. A Configuration Array is used to map the absolute address of the key region in to its physical address. The absolute address of keys can be fixed even though the physical location of the keys is relocated into a different region. A triple-detect double correct ECC scheme is used to protect keys. The ECC scheme is different from regular data in the storage and can be used to detect illegal access. Extra firmware and hardware is also designed to restrain customer's applications from directly accessing keys. With the key region being relocatable, the firmware could move the key region away from a known faulty area in a memory to improve system RAS. We also achieved the commonality objective that key memory device can use the same memory devices with other server systems that do not use keys.

Relocatable storage protect keys for system main memory

A DDR SDRAM DIMM for a mainframe main storage subsystem has a plurality of DDR SDRAMs on a rectangular printed circuit board having a first side and a second side, a length (152 MM=6 inch) between 149 and 153 millimeters and optimized at 149.15 mm or 151.35 mm in length and first and second ends having a width smaller than the length; a first plurality of connector locations on the first side extending along a first edge of the board that extends the length of the board, a second plurality of connector locations of the second side extending on the first edge of the board, a locating key having its center positioned on the first edge and located between 80 mm and 86 mm and optimized with a locating key 1.5 mm wide centered at 81.58 or 85.67 mm from the first end of the board and located between 64 and 70 mm and optimized with the locating key centered at 67.58 or 65.675 from the second end of the board. Each DIMM has memory regions comprising one of a plurality of physical entities hereafter referred to as memory macros which are relocatable regions which contain SP Keys and data set storage in the DIMM physical memory. These memory macros SP Key regions define an arbitrary logic structure for main storage which has a hard physical boundary.

Processor memory array having memory macros for relocatable store protect keys

A memory subsystem that includes segment level sparing. The memory subsystem includes a cascaded interconnect system with segment level sparing. The cascaded interconnect system includes two or more memory assemblies and a memory bus. The memory bus includes multiple segments and the memory assemblies are interconnected via the memory bus.

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Poughkeepsie, NY, United States of America

Kevin W Kark