Unisys Corporation

Digital Equipment Corporation

Other

Hewlett-packard Development Company, L.P.

Kevin W Harris

Andrew T Jennings

Charles R Caldarale

Maurice Marks

William B Noyce

Steven O Hobbs

Brian F Wibecan

Curt K Burmeister

John A Bircsak

Gregory Heimann

Systems and methods for executing non-native instructions in a computing system having a processor configured to execute native instructions are provided. A dynamic translator uses instruction code translation in parallel with just-in-time (JIT) compilation to execute the non-native instructions. Non-native instructions may be interpreted to generate instruction codes, which may be stored in a shadow memory. During a subsequent scheduling of a non-native instruction for execution, the corresponding instruction code may be retrieved from the shadow memory and executed, thereby avoiding reinterpreting the non-native instruction. In addition, the JIT compiler may compile instruction codes to generate native instructions, which may be made available for execution, further speeding up the execution process. A system implementing the aforementioned translator may improve performance and speed associated with executing non-native instructions by optimizing the use of instruction codes and JIT-compiled native instructions corresponding to the instruction codes when executing the non-native instructions.

Updating compiled native instruction paths

Defining an instruction path to be compiled by a just-in-time (JIT) compiler

Implementing a jump instruction in a dynamic translator that uses instruction code translation and just-in-time compilation

A method for executing non-native instructions in a computing system having a processor configured to execute native instructions may include fetching a first non-native instruction from a plurality of non-native instructions; interpreting the first non-native instruction to generate a first instruction code; compiling the first instruction code to generate a first native instruction corresponding to the first non-native instruction; determining whether to execute the first instruction code or the generated first native instruction; and implementing a first virtual machine instruction corresponding to the first non-native instruction based, at least in part, on determining whether to execute the first instruction code or the first native instruction.

Just-in-time dynamic translation for translation, compilation, and execution of non-native instructions

Dynamic on/off just-in-time compilation in a dynamic translator using instruction code translation

The invention comprises a technique for allocating memory in a multiprocessing computing system. In a first aspect, a method in accordance with the present invention begins by collecting a plurality of descriptions of shared data items. The shared data items are then dynamically allocated into a local virtual address space shared by a plurality of CPUs within a single node. The description of this allocation is the then stored. The method then accesses the stored allocation description to determine the virtual memory address of a shared data item. Whenever a data request is generated, it is determined from this virtual memory address whether the shared data item is available within the shared local virtual address space. If so, the access is performed in the shared local virtual address space. If the data is unavailable in the local virtual address space, it is accessed from a remote memory space.

Technique for referencing distributed shared memory locally rather than remotely

A system and method for controlling execution of nested loops in parallel in a computer including multiple processors, and a compiler for generating code therefor. The code enables the computer to operate in the following manner. Each processor processes an iteration of an outer loop in a set of nested loops. If the outer loop contains more iterations than processors in the system, the processors are initially assigned early iterations, and the later iterations are assigned to the processors as they finish their earlier iterations, until the processors have processed all of the iterations. Each processor, during processing of an outer loop iteration runs the iterations comprising the inner loop serially. In order to enforce dependencies between the loops, each processor reports its progress in its iterations of the inner loop to the processor executing the succeeding outer loop iteration. In addition, each processor, before processing the inner loop iterations of an assigned outer loop iteration, determines whether the processor computing the preceding outer loop is ahead or behind in processing its inner loop iteration by an amount which guarantees that dependencies will be enforced.

System and method for controlling execution of nested loops in parallel

A compiler includes a register allocation method making use of the concept of assigning temporary items to lifetime holes if such holes exist that are suitable. The compiler includes a front end for converting the input code to an intermediate representation, then this input representation is traversed to identify all of the temporary items, and to find all of the holes in the temporary items. Lists are maintained of the identified temporaries and holes. Register allocation then includes assigning temporaries to registers so long as there are free registers, and if holes are available in already-assigned temporaries then these holes are used in assigning registers. After all the available registers and holes are used, remaining temporaries are unallocated and thus represent memory references.

Compiler allocating a register to a data item used between a use and

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Nashua, NH, United States of America

Kevin W Harris