Intel Corporation

Kevin W Bross

Glen J Anderson

Gregory A Peek

Rakesh Dodeja

David I Poisner

Ravishankar Iyer

Anand S Konanur

Tomer Rider

Omesh Tickoo

Meng Shi

Mark R Francis

Neelam Chandwani

Ankur Agrawal

Udayan Mukherjee

Shawn S Mceuen

Nagabhushan Chitlur

Chetan Hiremath

Gene F Young

Rebecca Chierichetti

Ashok Sunder Rajan

Wen Wei

Robert J Hunter

Yevgeniy Y Yarmosh

David A Baker

Blanka Vlasak

Hemaprabhu Jayanna

William J Tiso

Therese E Dugan

Dirk Blevins

Manishkumar T Rana

John Gaffrey

Benjamin Cheong

Todd Langley

Monte G Johnson

Jonathan Gitlin

Andrew M Monk

April E Fisher

Alex deVries

David A De Vries

Cory A Harris

Pearl N Olanrewaju

Sudeep Puligundla

Examples described herein are used in timing synchronization systems. A timing synchronization system provides circuits that support bi-directional half-duplex voltage signals (transmit or receive) but protect against incorrect input/output configuration whereby a transmit signal media is connected to a receive port or a receive signal media is connected to a transmit port. The system provides configurable signal propagation by use of parallel connection of two or more buffer in series with a resistor. Various isolation circuitry and resistors can be used to protect against signal transmission during receive mode.

Bi-directional buffer with circuit protection time synchronization

Apparatuses and systems associated with expansion card design with a coherent connector to provide for coherent communication are disclosed herein. In embodiments, a circuit card may comprise an integrated circuit (IC), a first connector to couple the IC to a processor of a computer device, the first connector to provide for non-coherent communication between the IC and the processor, and a second connector to couple the IC to the processor, the second connector to provide for coherent communication between the IC and the processor. Other embodiments may be described and/or claimed.

Circuit card with coherent interconnect

Technologies for structured media playback include one or more physical media objects, which may be placed on a substrate including a matrix of position sensor tags. Each of the physical media objects is configured to sense one or more position sensor tags and transmit tag information received from the sensed position sensor tags to a compute device. The compute device determines a cast of physical media objects present on the substrate based on the received tag information and selects media for playback based on the determined cast. In some embodiments, the compute device may select the index of the media at which to initiate playback based on the determined cast or collection of physical media objects.

Technologies for structured media playback

Technologies for physical programming include a model compute system to determine one or more physical blocks assembled in a constructed model. The model compute system determines rules associated with the one or more physical blocks in which at least one rule defines a behavior of the constructed model and determines a program stack for execution by the model compute system based on the rules associated with the one or more physical blocks.

Technologies for physical programming

An embodiment of the invention allows a network access server to control network access for individual applications that run on a device. The device may be included in a machine-to-machine environment. The embodiment may provide a secure channel between the network access server and the device access layer and another secure channel between the device access layer and the device application layer. Thus, before applications are allowed to access the network those applications may be required to authenticate themselves via a secure channel. Other embodiments are described herein.

Secure machine to machine communication

Control of an apparatus is provided according to determination of positioning of information pieces with radio frequency identification (RFID) tags. In embodiments, an apparatus may include one or more pieces, wherein each piece may be positionable in one or more piece positions of a region and may include a passive RFID tag that stores information relating to a characteristic of the piece. An arrangement of RFID antennas may be positioned proximal to the region, and a RFID reader may provide reads of the pieces near the RFID antennas. One or more processors may determine the piece positions of the one or more pieces from the reads and may provide control of the apparatus according to the one or more pieces and their piece positions.

Position determination and control with radio frequency identification tags

A modeling module is disclosed that couples to a modular platform chassis. The modeling module includes a resident management controller to implement a test to model a component layout for a module to be received and coupled to the modular platform chassis. The test includes an operating thermal load for a component resident on the module at a given location. The module has a dimensional length and width that is similar to that of the modeling module. The modeling module also includes a thermal load device that is responsive to the management controller. The thermal load device is to implement at least a portion of the test by simulating the operating thermal load for the component resident on the module at the given location.

Modeling module

A method for receiving a signal from a local device and converting the signal to a network port packet data signal to emulate a local data signal port. Once the signal from the local device is converted to the network port packet data signal, the network port packet data signal is transmitted to a remote device over a network connection.

Method and apparatus for emulating a local data port

An integrated circuit having a non-volatile HGRAM cell includes a first section having impurity materials implanted into a substrate to form NPN transistor regions and a second section having a gate structure to control the currents conducted in the NPN transistor regions. The gate structure is formed at least above the P-type channel region of the substrate and includes an hourglass shaped material with gates to control the movement of holes through the restricted portion of the hourglass.

Hourglass ram

According to some embodiments, an apparatus includes a chassis to house a plurality of electronic cards, a backplane housed in the chassis, and a fan housed in the chassis. A first portion of the fan may be lower than a top edge of the backplane, and a second portion of the fan may be higher than the top edge of the backplane.

Chassis cooling system

Dynamic switching between mirrored and non-mirrored implementations is provided by formatting a system to operate in a simulated mirrored mode. A null location is used as a placeholder for a storage location that can be subsequently added. The null location is replaced in whole or in part by the storage location when actual mirrored node is desired, thereby making the switch to actual mirrored mode appear dynamic and transparent to a user. A first location is designated as a first part of a mirror, and the null location is designated to simulate a second part of the mirror. Data and/or operating systems may be mirrored.

Method and apparatus for dynamic mirroring availability in a network appliance

Growing community of inventors

Beaverton, OR, United States of America

Kevin W Bross