International Business Machines Corporation

Kevin W Brew

Injo Ok

Michael S Gordon

Clifford A Pickover

James R Kozloski

Timothy Mathew Philip

Nicole A Saulnier

Teodor Krassimirov Todorov

Seyoung Kim

Talia S Gershon

Lawrence Alfred Clevenger

Dennis Merton Newns

Iqbal Rashid Saraf

Wei Wang

Jin Ping Han

Balasubramanian Pranatharthiharan

Heng Wu

Ashish Kundu

Saurabh Singh

Tian Shen

Devendra K Sadana

Takashi Ando

Ning Li

Jingyun Zhang

Andrew Herbert Simon

Oki Gunawan

Muthumanickam Sankarapandian

Matthew Joseph BrightSky

Ruilong Xie

Effendi Leobandung

Guy M Cohen

Ruqiang Bao

Praneet Adusumilli

Joel Pereira De Souza

Sanjay C Mehta

Yun Seog Lee

Robert L Bruce

Lan Yu

Ching-Tzu Chen

Prasad Bhosale

Ryan T Gordon

Steven Michael McDermott

Jerry D Tersoff

Kangguo Cheng

Carl John Radens

Stephen W Bedell

Michael Rizzolo

Reinaldo Ariel Vega

Robert Russell Robison

Nicholas Anthony Lanzillo

Brian Paul Gaucher

Glenn John Martyna

Nanbo Gong

Youngseok Kim

Ardasheir Rahman

Adra Carr

Hari Prasad Amanapu

Maruf Amin Bhuiyan

Anirban Chandra

Mattias Fitzpatrick

Singh Saurabh

Steven M Mcdermott

Caitlin Camille Stuckey

Rebecca Colby Martin

A plurality of bit lines corresponding to elements of an input vector intersect a plurality of word lines and a plurality of memristive cells are located at the intersections. At least three cells are grouped together to represent a single matrix element. At least three word lines correspond to each element of an output vector. An A/D converter is coupled to each of the word lines, and for each line, except a first, in each group, a shifter has an input coupled to one of the A/D converters. For each group, an addition-subtraction block adds the output of the A/D converter coupled to the first one of the word lines to outputs of each of the shifters except that for a last one of the word lines, subtracts the output of the last shifter, and outputs a corresponding element of an output vector.

Digital phase change memory (PCM) array for analog computing

A semiconductor component includes a dielectric layer including an opening. The semiconductor component further includes a liner arranged in the opening in direct contact with the dielectric layer. The semiconductor component further includes a wetting layer arranged in the opening in direct contact with the liner. The semiconductor component further includes an interconnect structure arranged in the opening in direct contact with the wetting layer. The semiconductor component further includes a cap arranged in the opening in direct contact with the interconnect structure and separated from the wetting layer by a spacer.

Damascene interconnect spacer to facilitate gap fill

A heater, a system, and a method for linearly changing the resistance of the phase change memory through a graded heater. The system may include a phase change memory. The phase change memory may include a dielectric. The phase change memory may also include a heater patterned on the dielectric, the heater including: an outside conductive heating layer that has a higher resistance than other layers of the heater, and an inside conductive heating layer that has a lower resistance than the outside conductive heating layer, where the outside conductive heating layer is at an outside area of the heater and the inside conductive heating layer is at an inside area of the heater. The phase change memory may also include a phase change material proximately connected to the heater. The phase change memory may also include a top electrode proximately connected to the phase change material.

Phase change memory with graded heater

A phase change memory (PCM) cell includes a first electrode comprised of a first electrically conductive material, a second electrode comprised of a second electrically conductive material, and a phase change section positioned between the first electrode and the second electrode. The phase change section includes a first phase change material having a first resistance drift coefficient, and a second phase change material having a second resistance drift coefficient that is greater than the first resistance drift coefficient. An axis of the PCM cell extends between the first electrode and the second electrode, and the second phase change material is offset from the first phase change material in a direction that is perpendicular to the axis.

Composite material phase change memory cell

Embodiments described herein provide for integrated input/output and logic devices for nanosheet technology and methods of fabrication for the devices. The types of transistors used for input/output devices and logic devices may differ such that, for example, input/output devices may use EG (Extended Gate) Field Effect Transistors (FET) while logic devices may use Suspended Gate (SG) FETs. Co-locating SG and EG devices on a single die provides for a fabricator to assure alignment between the nanosheets used in the SG and EG devices (improving consistency in the device characteristics on a single die) and reduce overall space requirements for the hardware used by input/output and logic devices.

Integrated input output and logic device for nanosheet technology

A computer memory device includes a bottom electrode, a top electrode, and a memory component arranged between the top electrode and the bottom electrode. The memory component is made of a dielectric solid-state material and is in direct contact with the top electrode and the bottom electrode. The computer memory device further includes a proximity heater configured to increase a temperature of a portion of the memory component. The computer memory device further includes a layer of dielectric material in direct contact with the proximity heater. The layer of dielectric material is in direct contact with one of the bottom electrode and the top electrode.

Proximity heater to lower RRAM forming voltage

A method is presented for reducing a reset current for a phase change memory (PCM). The method includes forming a bottom electrode, constructing a PCM cell structure including a plurality of phase change memory layers and a plurality of heat transfer layers, wherein the plurality of phase change memory layers are assembled in an alternating configuration with respect to the plurality of heat transfer layers, and forming a top electrode over the PCM cell structure. The plurality of phase change memory layers are arranged perpendicular to the top and bottom electrodes. Additionally, airgaps are defined adjacent the PCM cell structure.

Phase change memory using multiple phase change layers and multiple heat conductors

Described are techniques for corroborating anomalous behavior. The techniques include training devices included in an Internet of Things (IoT) mesh network to independently identify occurrences of anomalous behavior in a proximate physical environment. The techniques further include receiving event data from at least a portion of the devices in the IoT mesh network corresponding to a time window, where the event data reports occurrences of at least one type of anomalous behavior. The techniques further include corroborating the at least one type of anomalous behavior to determine that the occurrences of the at least one type of anomalous behavior indicate an anomalous event that meets a reporting threshold for providing notice of the anomalous event. The techniques further include generating a notification regarding the anomalous event.

Corroborating device-detected anomalous behavior

A first phase change material layer vertically aligned above a bottom electrode, a dielectric layer vertically aligned above the first phase change material layer, a second phase change material layer vertically aligned above the dielectric layer, an inner electrode physically and electrically connected to the first phase change material layer and the second phase change material layer, the inner electrode surrounded by the dielectric layer, a top electrode vertically aligned above the second phase change material layer. A first phase change material layer vertically aligned above a bottom electrode, a filament layer vertically aligned above the first phase change material layer, a second phase change material layer vertically aligned above the filament layer, an inner break in the filament layer connecting the first phase change material layer and the second phase change material layer, a top electrode vertically aligned above the second phase change material layer.

Phase change memory cell with double active volume

Methods for setting a resistance include applying a voltage across a memristive device, that exceeds a threshold based on a difference in chemical potential between a first material and a second material, to change a resistance of the memristive device. The memristive device includes a barrier layer of the second material that is formed between two metastable layers of the first material.

Two-terminal metastable mixed-conductor memristive devices

A memory, system, and method to improve integration density while maintaining thermal efficiency through a phase change memory cell with a superlattice based thermal barrier. The phase change memory may include a bottom electrode. The phase change memory may also include an active phase change material. The phase change memory may also include a superlattice thermal barrier proximately connected to the active phase change material. The phase change memory may also include a top electrode proximately connected to the superlattice thermal barrier. The system may include the phase change memory cell. The method for forming a phase change memory may include depositing an active phase change material on a bottom electrode. The method may also include depositing a superlattice thermal barrier proximately connected to the active phase change material. The method may also include depositing a top electrode proximately connected to the superlattice thermal barrier.

Phase change memory cell with superlattice based thermal barrier

A phase change memory, a system, and a method to prevent high resistance drift within a phase change memory through a phase change memory cell with three terminals and self-aligned metal contacts. The phase change memory may include a bottom electrode. The phase change memory may also include a heater proximately connected to the bottom electrode. The phase change memory may also include a phase change material proximately connected to the heater. The phase change memory may also include metal proximately connected to at least two sides of the phase change material. The phase change memory may also include three terminals, where a bottom terminal is located at an area proximately connected to the heater and two top terminals are located at areas proximately connected to the metal.

Three terminal phase change memory with self-aligned contacts

A semiconductor structure includes a first electrode; a second electrode; a dielectric material between the first electrode and the second electrode, the dielectric material having at least one wall extending from the first electrode to the second electrode to define a void within the dielectric material and between the first electrode and the second electrode; and a layer of phase change material on the at least one wall of the dielectric material and in contact with the first electrode and the second electrode.

Electronic fuse with passive two-terminal phase change material and method of fabrication

A phase change memory bridge cell comprising a dielectric layer located on top of a at least one electrode, wherein a trench is located in the dielectric layer. A first liner located at the bottom of the trench in the dielectric layer and the first liner is located on the sidewalls of the dielectric layer that forms the sidewalls of the trench. A phase change memory material located on top of the first liner, wherein a top surface of the phase change memory material is aligned with a top surface of the dielectric layer, wherein the dielectric layer is located adjacent to and surrounding the vertical sidewalls of the phase change memory material, wherein a top surface of the phase change memory material is flush with a top surface of the dielectric layer.

Confined bridge cell phase change memory

Insulated phase change memory devices are provided that include a first electrode; a second electrode; a phase change material disposed in an electrical path between the first electrode and the second electrode; and a porous dielectric configured to concentrate heat produced by a reset current carried through the phase change material between the first electrode and the second electrode to mitigate an amount of heat that escapes from the phase change material. The porous dielectric may be an inherently porous dielectric material or a dielectric material in which porous structures are induced during fabrication. Methods of fabrication of such devices are also provided.

Insulated phase change memory using porous dielectrics

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Kevin W Brew