Hewlett Packard Enterprise Development LP

Hewlett-packard Development Company, L.p.

Kevin T Lim

Parthasarathy Ranganathan

Jichuan Chang

Alvin AuYoung

Sheng Li

Partha Ranganathan

Yoshio Frank Turner

Jose Renato G Santos

Mitchel E Wright

Norman Paul Jouppi

Dejan S Milojicic

Paolo Faraboschi

Naveen Muralimanohar

Robert S Schreiber

Mark David Lillibridge

Jeffrey Clifford Mogul

Alistair Veitch

William C Hallowell

Raghavan V Venugopal

Reza Mushtag Bacchus

Jishen Zhao

Jim W Brainard

Muhuan Huang

Sai Rahul Chalamalasetti

Onur Kocberber

Hubert E Brinkmann, Jr

A system and method for retrieving cached data are disclosed herein. The system includes a cache server including a local memory and a table residing on the local memory, wherein the table is used to identify data objects corresponding to cached data. The system also includes the data objects residing on the local memory, wherein the data objects contain pointers to the cached data. The system further includes a remote memory communicatively coupled to the cache server through an Input-Output (I/O) connection, wherein the cached data resides on the remote memory.

Data caching using local and remote memory

Disclosed herein are a system, non-transitory computer readable medium, and method for governing communications of a bare metal guest in a cloud network. A network interface handles packets of data in accordance with commands by a control agent.

Governing bare metal guests

Methods, systems, and computer-readable and executable instructions are provided for checkpointing using a field programmable gate array (FPGA). Checkpointing using FPGA can include checkpointing data within a region of a server's contents to memory and monitoring the checkpointed data using the FPGA.

Checkpointing using FPGA

According to an example, a processor generates a memory access request and sends the memory access request to a memory module. The processor receives data from the memory module in response to the memory access request when a memory device in the memory module for the memory access request is busy and unable to execute the memory access request.

Memory access for busy memory by receiving data from cache during said busy period and verifying said data utilizing cache hit bit or cache miss bit

An example system includes a memory controller; a memory bus coupled to the memory controller; and a dual inline memory module (DIMM) coupled to the memory controller through the memory bus. The DIMM includes a dynamic random access memory (DRAM) portion; a storage portion; and a gate array portion coupled to the memory bus to detect memory access signals and to store information related to the memory access signals on the storage portion.

Memory access signal detection utilizing a tracer DIMM

A technique includes acquiring a plurality of write requests from at least one memory controller and logging information associated with the plurality of write requests in persistent storage. The technique includes applying the plurality of write requests atomically as a group to persistent storage.

Atomically committing write requests

A bit vector for a Bloom filter is determined by performing one or more hash function operations on a set of ternary content addressable memory (TCAM) words. A TCAM array is partitioned into a first portion to store the bit vector for the Bloom filter and a second portion to store the set of TCAM words. The TCAM array can be searched using a search word by performing the one or more hash function operations on the search word to generate a hashed search word and determining whether bits at specified positions of the hashed search word match bits at corresponding positions of the bit vector stored in the first portion of the TCAM array before searching the second portion of the TCAM array with the search word.

Partitionable ternary content addressable memory (TCAM) for use with a bloom filter

One embodiment is a storage system having one or more compute blades to generate and use data and one or more memory blades to generate a computational result. The computational result is generated by a computational function that transforms the data generated and used by the one or more compute blades. One or more storage devices are in communication with and remotely located from the one or more compute blades. The one or more storage devices store and serve the data for the one or more compute blades.

Storage system with a memory blade that generates a computational result for a storage device

A replace operation is performed in relation to a priority queue. The priority queue has trees and elements. A first element stores a value having a greatest priority of any value stored in any element and in any tree. Each tree corresponds to one of the elements.

Priority queue having array and trees

A memory server providing remote memory for servers independent from the memory server. The memory server includes memory modules and a page table. A memory controller for the memory server allocates memory in the memory modules for each of the servers and manages remote memory accesses for the servers. The page table includes entries identifying the memory module and locations in the memory module storing data for the servers.

Memory server

According to an example, data for a memcached server is replicated to a memcached replication server. Data operations for the memcached server may be filtered for backing up data to the memcached replication server.

Memcached server replication

A method of accessing remote memory comprising receiving a request for access to a page from a computing device, adding an address of the accessed page to a recent list memory on the remote memory, associating a recent list group identifier to a number of addresses of accessed pages, transferring the requested page to the computing device with the recent list group identifier and temporarily maintaining a copy of the transferred page on the remote memory.

Accessing remote memory on a memory blade

Reconfigurable crossbar networks, and devices, systems and methods, including hardware in the form of logic (e.g. application specific integrated circuits (ASICS)), and software in the form of machine readable instructions stored on machine readable media (e.g., flash, non-volatile memory, etc.), which implement the same, are provided. An example of a reconfigurable crossbar network includes a crossbar. A plurality of endpoints is coupled to the crossbar. The plurality of endpoints is grouped into regions at design time of the crossbar network. A plurality of regional interconnects are provided. Each regional interconnect connects a group of endpoints within a given region.

Reconfigurable crossbar networks

A method of using a buffer within an indexing accelerator during periods of inactivity, comprising flushing indexing specific data located in the buffer, disabling a controller within the indexing accelerator, handing control of the buffer over to a higher level cache, and selecting one of a number of operation modes of the buffer. An indexing accelerator, comprising a controller and a buffer communicatively coupled to the controller, in which, during periods of inactivity, the controller is disabled and a buffer operating mode among a number of operating modes is chosen under which the buffer will be used.

Growing community of inventors

La Honda, CA, United States of America

Kevin T Lim